This chapter describes the Pixel Clock Synthesizer, device U1601 on the upper board.
The Pixel Clock Synthesizer is a phase locked loop (PLL) frequency synthesizer providing differential pixel clock outputs. The Pixel Clock Synthesizer generates a wide range of pixel clock frequencies under control of LeoCross.
The OSC_SEL(3:0) and OSC_STB_L signals are used to load the synthesizer's control registers, as shown in Figure 11-1. LeoCross places the address of the register to be loaded on the OSC_SEL(3:0) lines and asserts the OSC_STB_L signal. The negative edge of OSC_STB_L latches the address into the synthesizer. LeoCross then places the data to be loaded into the selected register on the OSC_SEL(3:0) lines and deasserts OSC_STB_L. The positive edge of OSC_STB_L latches the data into the register.
Figure 11-1 Synthesizer Addressing
The synthesizer, shown in simplified form in Figure 11-2, generates pixel clock frequencies using phase-locked loop (PLL) techniques. The phase-locked loop is a closed-loop feedback system that drives the output frequency to be ratiometrically related to the reference frequency provided by the 13.5 MHz crystal.
Figure 11-2 Pixel Clock Synthesizer Simplified Block Diagram
The Phase Frequency Detector, shown in Figure 11-2, drives the VCO (voltage controlled oscillator) to a frequency that causes the two inputs to the Phase Frequency Detector to be matched in frequency and phase. This occurs when:
where
N = Feedback divider
R = Reference divider
The reference divider, R, may be programmed for any modulus from 1 to 128 in steps of 1.
The feedback divider, N, may be programmed for any modulus from 37 through 448 in steps of 1. The feedback divider uses a dual-modulus prescaler, the A and M counters, that allows the programmable counters to operate at low frequencies. The A and M counters are programmable via the OSC_SEL(3:0) inputs.
The equation for determining the feedback divider is:
N = [6(M + 1)] + A
except when A = 0, then:
N = 7(M + 1)
The VCO gain is also programmable, expressed in MHz/volt. See Table 11-2 on page 11-5.
The Pixel Clock Synthesizer contains 16 registers, which are described in Table 11-1.
Table 11-1 Pixel Clock Synthesizer Registers
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Register Bits Register Description No. Bits --------------------------------------------------------------------------------------
0 0 - 3 R(0) - R(3) Reference divider (R) modulus control bits 0 - 3.
Modulus = value + 1
1 0 - 2 R(4) - R(6) Reference divider (R) modulus control bits 4 - 6.
2 0 - 3 A(0) - A(3) Feedback divider "A" counter control. When set to 0,
modulus = 7. Otherwise, modulus = 7 for value
underflows of the prescaler, and modulus = 6
thereafter until "M" counter underflows.
3 0 - 3 M(0) - M(3) Feedback divider "M" counter control bits 0 - 3.
Modulus = value + 1.
4 0 - 1 M(4) - M(5) "M" counter control bits 4 - 5.
4 2 - 3 Not used for Leo.
5 0 - 3 Not used for Leo.
6 0 - 3 Not used for Leo.
7 0 - 3 Not used for Leo.
8 3 Not used for Leo.
8 0 - 2 V(0) - V(2) VCO gain. See Table 11-2.
9 0 - 1 P(0) - P(1) Phase detector gain. Set to 1 for Leo.
9 2 - 3 Not used for Leo.
11 0 - 1 S(0) - S(1) Post scaler. See Table 11-3. Normally set to 0 for Leo.
12 0 - 3 Not used for Leo.
15 3 PDRSTEN Phase-detector reset enable. Set to 0 on Leo.
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After power up, the synthesizer requires 32 register writes for new programming to become effective. Since the synthesizer has only 13 registers, programming requires 19 dummy writes. The dummy writes can be to register 13 or 14 (unused registers).
Table 11-2 shows how the VCO gain bits control VCO gain.
Table 11-2 VCO Gain
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V(2) V(1) V(0) VCO Gain (MHz/Volt) ---------------------------
1 0 0 30
1 0 1 45
1 1 0 60
1 1 1 80
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Table 11-3 shows how the post scaler select bits work.
Table 11-3 Post Scaler
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S(1) S(2) Description ---------------------------
0 0 Post-scaler = 1
0 1 Post scaler = 2
1 0 Post scaler = 4
1 1 Not used
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Table 11-4 shows example register settings for several standard pixel clock frequencies.
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Screen Resolution Pixel Clock Register Number Frequency (MHz) ------------------------------------------------------------------------------
0 1 2 3 8 9 ------------------------------------------------------------------------------
640 \xb4 480 @ 60 Hz (NTSC) 12.272727 5 1 2 2 4 1
770 \xb4 576 @ 50 Hz (PAL) 14.75 5 3 5 8 4 1
15.0 1 1 2 2 4 1
54.0 4 0 2 2 4 1
1024 \xb4 768 @ 60 Hz (VGA) 64.125 MHz 3 0 1 2 4 1
1024 \xb4 768 @ 70 Hz (VGA) 74.25 5 0 3 4 4 1
84.375 3 0 1 3 4 1
1152 \xb4 900 @ 66 Hz 93.0 8 0 2 9 4 1
1152 \xb4 900 @ 66 Hz (alternate) 94.5 1 0 0 1 4 1
960 \xb4 680 @ 108 Hz (stereo) 99.900002 4 0 1 5 4 1
960 \xb4 680 @ 112 Hz (stereo) 101.25 5 0 3 6 5 1
1152 \xb4 900 @ 76 Hz 105.75 5 0 5 6 5 1
1280 \xb4 1025 @ 60 Hz 108.0 3 0 2 4 5 1
1280 \xb4 1024 @ 67 Hz 117.0 2 0 2 3 5 1
1280 \xb4 1024 @ 67 Hz (alternate) 118.125 3 0 0 4 5 1
1280 \xb4 1024 @ 76 Hz 135.0 3 0 4 5 6 1
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