10 Output RAMDAC





This chapter describes the output digital-to-analog converter (RAMDAC).

10.1 Introduction

The Output RAMDAC, U1501 on upper board schematic, is an Analog Devices ADV7152 "True-Color Graphics" 10-bit video RAMDAC. The RAMDAC, shown in Figure 10-1, contains three 10-bit video digital-to-analog converters (one each for R, G, and B), three 256 by 10 (or one 256 by 30) color look-up tables, palette priority registers, a pixel input data multiplexer/serializer, and a clock generator/divider serializer circuit.

The RAMDAC is capable of either one-to-one multiplexing or two-to-one multiplexing. Leo uses the two-to-one multiplexing capabilities.

The individual R, G, and B pixel input ports from LeoCross allow 24-bit true color image rendition. The true color rendition is achieved through the on- chip data multiplexer/serializer. The 30 bits of resolution out of the color palette and the triple 10-bit DAC stage realizes 24-bit true color while also allowing for color correction.

    Figure 10-1 Output RAMDAC Block Diagram

10.2 Pin Descriptions

The RAMDAC has four interfaces: LeoCross, CX Bus, video output, and clock input.

10.2.1 LeoCross Interface

Table 10-1 summarizes the RAMDAC LeoCross interface signals.

    Table 10-1 RAMDAC LeoCross Interface Signals

-----------------------------------------------------------------------
Signal Name No. Pins I/O Type Description -----------------------------------------------------------------------
                                       
RA<7:0'>      8         I    Tri-state  Red color, A input - DAC_A<23:16'>
                                       
GA<7:0'>      8         I    Tri-state  Green color, A input - DAC_A<15:8'>
                                       
BA<7:0'>      8         I    Tri-state  Blue color, A input - DAC_A<7:0'>
                                       
RB<7:0'>      8         I    Tri-state  Red color, B input - DAC_B<23:16'>
                                       
GB<7:0'>      8         I    Tri-state  Green color, B input - DAC_B<15:8'>
                                       
BB<7:0'>      8         I    Tri-state  Blue color, B input - DAC_B<7:0'>
                                       
LD_IN        1         I    Tri-state  DAC load (comes from DAC_LD)
                                       
LD_OUT       1         O    Bi-state   Pixel clock divided by 2
                                       
SYNC_L       1         I    Tri-state  Video composite sync
                                       
BLANK_L      1         I    Tri-state  Video composite blank

-----------------------------------------------------------------------

10.2.1.1 RA<7:0 through BB<7:0'>

The color inputs from LeoCross. LeoCross performs a five-to-two interleave conversion. The two RAMDAC inputs represent two adjacent pixels.

On the schematic, these signals are DAC_A<23:0 and DAC_B<23:0. The correlation between the schematic signals and the RAMDAC inputs are as follows:

----------------------------------------------
Schematic RAMDAC Schematic RAMDAC ----------------------------------------------
                                       
DAC_A<23:16    RA<7:0'>   DAC_B<23:16'>   RB<7:0'>
                                       
DAC_A<15:8'>   GA<7:0'>   DAC_B<15:8'>    GB<7:0'>
                                       
DAC_A<7:0'>    BA<7:0'>   DAC_B<7:0'>     BB<7:0'>

----------------------------------------------

10.2.1.2 LD_IN

DAC load. The rising edge of LD_IN latches the RGB inputs and the BLANK and SYNC signals into the DAC.

10.2.1.3 LD_OUT

The load-out signal. Generated by the PIX_CLK (pixel clock) inputs, the LD_OUT signal is pixel clock divided by two. The output clock actually comes from a variable divider, within the RAMDAC, that is controlled by a register value (see "Pixel Multiplexer Control" on page 10-18).

10.2.1.4 SYNC_L

Video composite sync signal from LeoCross. Drives the IOG analog video output to the sync level (see Figure 10-2 on page 10-7).

10.2.1.5 BLANK_L

Video composite blank signal from LeoCross. Drives the analog video outputs to the blanking level (see Figure 10-2 on page 10-7).

10.2.2 CX Bus Interface

Table 10-2 summarizes the CX Bus interface signals. See Chapter 5, "CX Bus," for more information on the CX Bus interface.

    Table 10-2 RAMDAC CX Bus Interface Signals

----------------------------------------------------------------
Signal Name No. Pins I/O Type Description ----------------------------------------------------------------
                                       
D<9:0'>       10        I/O  Tri-state  CX address and data bus
                                       
CE*          1         I    Bi-state   Output DAC chip enable
                                       
R/W*         1         I    Bi-state   CX Bus read or write enable
                                       
C<1:0'>       2         I    Bi-state   CX Bus control

----------------------------------------------------------------

10.2.2.1 D<9:0'>

The RAMDAC data bus (the CX address and data bus). Data is written to and read from the RAMDAC over this 10-bit bidirectional data bus. Only eight of the 10 bits are used in Leo.

10.2.2.2 CE_L

The chip enable line for the Output RAMDAC. When asserted, the Output RAMDAC monitors the CX Bus for requested activities.

10.2.2.3 R/W_L

Transaction direction control (read or write). When this signal is low (write), LeoCommand drives the CX Bus. The enabled device takes the bus information and performs a write operation to the specified register or table.

When this signal is high, LeoCross performs the read cycle. Within a specified number of clock cycles, LeoCross or the Output RAMDAC drives its requested data, set by its internal address register, onto the CX Bus.

10.2.2.4 C<1:0'>

Control bits. These signals are derived from the SBus address and are used to differentiate between direct and indirect accesses. They also provide the direct access device address. Table 10-3 defines the control signals.

    Table 10-3 CX Bus RAMDAC Control Signals

-----------------------------------------------
Select C1 C0 Description Access -----------------------------------------------
                                         
RAMDAC  0   0   RAMDAC address pointer   Direct
                                         
RAMDAC  0   1   RAMDAC color table       Indirect
                                         
RAMDAC  1   0   RAMDAC control register  Indirect
                                         
RAMDAC  1   1   RAMDAC mode register     Direct

-----------------------------------------------

10.2.3 Video Output

Table 10-4 summarizes the video output signals.

    Table 10-4 RAMDAC Video Output Signals

----------------------------------------------------------------------------------
Signal Name No. Pins I/O Type Description ----------------------------------------------------------------------------------
                                      
IOR          1         O    Bi-state  Analog video current output for red channel 
                                      (DAC_RED).
                                      
IOG          1         O    Bi-state  Analog video current output for green channel 
                                      (DAC_GRN).
                                      
IOB          1         O    Bi-state  Analog video current output for blue channel 
                                      (DAC_BLU).

----------------------------------------------------------------------------------

Figure 10-2 shows the analog video output waveform.

    Figure 10-2 RAMDAC Analog Video Output Waveform

10.2.4 Clock Input

Table 10-5 summarizes the clock input signal.

    Table 10-5 RAMDAC Clock Input

-----------------------------------------------
Signal Name No. Pins I/O Type Description -----------------------------------------------
                                      
CLK & CLK_L   2         I    Bi-state  Pixel clock

-----------------------------------------------

10.2.4.1 CLK & CLK_L

The pixel clock. A differential clock generated by the pixel clock synthesizer (the PIX_CLK signals). The clock frequency is selectable by a register within LeoCross. For a definition of the frequency selections, see "OSC_SEL<4:0" on page 9-14.

10.3 Functional Description

The following paragraphs describe the RAMDAC chip in more detail.

10.3.1 CX Bus Interface

The CX Bus interface, shown in Figure 10-3, allows direct access to the RAMDAC internal control registers and the color palettes from LeoCommand. The CX_CTL1 and CX_CTL0 control inputs, in conjunction with the internal address register, specify which control register or color palette RAM entry is accessed.

    Figure 10-3 RAMDAC CX Bus Interface

10.3.2 LeoCross Interface

The LeoCross interface, shown in Figure 10-4, consists of two eight-bit RGB channels, which correspond to two consecutive pixels. The two-pixel channels are loaded simultaneously into the output RAMDAC by way of the LD_IN signal.

    Figure 10-4 LeoCross Interface

10.3.3 Switching Matrix and Pixel Mask

The switching matrix, under control of the command register, selects between 24-bit true color or eight-bit pseudo color.

10.3.3.1 24-Bit True Color Mode

In 24-bit true color mode, the color for each pixel is defined by the eight-bits- each red, green, and blue inputs from LeoCross, as shown in Figure 10-5.

    Figure 10-5 RAMDAC 24-Bit True Color Mapping

10.3.3.2 8-Bit Pseudo Color Mode

In eight-bit pseudo color mode, the color for each pixel is defined by eight bits on either the red, green, or blue inputs from LeoCross. Figure 10-6 shows the mapping for eight-bit pseudo color using the red channel. This method allows 256 colors to be displayed out of a total color palette of 16.7 million addressable colors.

    Figure 10-6 RAMDAC Eight-Bit Pseudo Color Mapping

10.3.4 Color Palette Tables

The RAMDAC has three 256-bit by 10-bit color lookup tables for gamma correction of the video output to allow for monitor errors in color presentation (non-linearity). The value stored at a given address in the palette RAM determines the color correction applied to the pixel.

The color palette may be programmed to be 24-bits deep (eight bits each for red, green, and blue) instead of 30 (ten bits each). When configured as 24 bits deep, the two least-significant bits of the ten-bit digital to analog converters are pulled down to zero, allowing for 256 output levels instead of 1024.

10.3.5 Digital to Analog Converter

On each clock cycle, the ten bits of color from each of the color palette RAMs are presented to the three ten-bit digital-to-analog converters. Each digital-to- analog converter converts the ten bit input to one of 1024 output levels. The CSYNC and CBLANK signals are pipelined through the RAMDAC to maintain synchronization with the pixel data. The resulting output is the composite video signal shown in Figure 10-2 on page 10-7.

The RAMDAC generates RGB video output signals that are compatible with RS-343A and RS-170 video standards.

10.4 RAMDAC Registers

The RAMDAC registers are accessible from the CX Bus. A few registers, like the address register, can be read or written directly (direct access). Others, like the color palette tables, are indirectly addressed via the address register.

Register access is affected by the CX Bus CX_CTL<1:0 bits, as follows:

----------------------------------------
C1 C0 Register Access Type ----------------------------------------
                              
0   0   Address register      Direct
                              
0   1   Color palette tables  Indirect
                              
1   0   Control registers     Indirect
                              
1   1   Mode register         Direct

----------------------------------------

10.4.1 Address Register

The address register, in conjunction with the C0 and C1 control bits, specify which control or mode register or color palette location is accessed by the CX Bus port. The address register is eight bits wide. When writing to or reading from the color palette on a sequential basis, only the start address needs to be written. After a red, green, and blue write sequence, the address register is automatically incremented.

10.4.2 Color Palette Tables

The color palette tables are 30 bits wide by 256 words (10 bits each for red, green, and blue, but only 8 bits are used). The color palette tables can also be configured as 24 bits each (eight bits each for red, green, and blue). When configured for 24 bits (8-bit mode), the unused bits are internally pulled down to zero.

To access the color palette tables requires several write operations. The first write is to the address register and specifies which of the 256 words is to be accessed.

The second through fourth accesses are to the red, green, and blue tables, respectively, as follows:

When writing to or reading from the color palette on a sequential basis, only the start address needs to be written. After a red, green, and blue access sequence, the address register increments automatically.

10.4.3 Control Registers

The RAMDAC has seven control registers. To access each register, two write operations must be performed. The first write to the address register specifies which of the seven registers is accessed. The second access determines the value written to the selected register.

The RAMDAC control registers are listed in Table 10-6.

    Table 10-6 RAMDAC Control Registers

-------------------------------------------------------
Addr. Reg (A2-A0) Control Registers -------------------------------------------------------
                   
0x0                Pixel test register
                   
0x1                DAC test register
                   
0x2                Sync, Blank, and IPLL test register
                   
0x3                ID register (read only)
                   
0x4                Pixel mask register
                   
0x5                Reserved
                   
0x6                Command register 2
                   
0x7                Command register 3

-------------------------------------------------------

10.4.4 Pixel Test Register

The pixel test register is used when the RAMDAC is in diagnostic mode. This is an eight-bit read-only register that allows CX Bus access to the pixel port. See "Diagnostic Modes" on page 10-20.

10.4.5 DAC Test Register

The DAC test register is used when the RAMDAC is in the diagnostic mode. This is a ten-bit read/write register that allows CX Bus access to the DAC port. See "Diagnostic Modes" on page 10-20.

10.4.6 Sync, Blank, IPLL Register

The Sync, Blank, IPLL Register is used when the RAMDAC is in the diagnostic mode. This is a three-bit read/write register that allows CX Bus access to these particular control bits. IPLL (actually written IPLL) is the RAMDAC phase lock loop output current. See "Diagnostic Modes" on page 10-20.

10.4.7 ID Register

The ID register is an eight-bit read-only register. For the ADV7152 RAMDAC, this register always returns the value 0x8C.

10.4.8 Pixel Mask Register

The contents of the pixel mask register are individually logically ANDed with the red, green, and blue pixel input stream of data. This is an eight-bit read/write register with D0 corresponding to R0, G0, and B0.

10.4.9 Command Register 2

Command register 2 contains eight control bits, as shown in Figure 10-7. Command register 2 is a ten-bit register, but only eight bits are used.

    Figure 10-7 RAMDAC Command Register 2 Format

10.4.9.1 R7 Trigger Polarity Control

This bit is used when the RAMDAC is in the diagnostic mode. See "Diagnostic Modes" on page 10-20. It determines whether the pixel data is latched into the test registers on the rising edge or falling edge of the R7 bit:

    0 = Rising edge
    1 = Falling edge

10.4.9.2 IPLL Trigger Control

This bit specifies whether the IPLL output is triggered from blank or sync:

    0 = Sync
    1 = Blank

10.4.9.3 Sync Recognition Control

This bit specifies whether the video sync input is to be encoded onto the IOG analog output or ignored:

    0 = Ignore
    1 = Decode

10.4.9.4 Pedestal Enable Control

This bit specifies whether a 0 IRE or a 7.5 IRE blanking pedestal is to be generated on the video outputs:

    0 = 0 IRE
    1 = 7.5 IRE

10.4.9.5 Color Mode Control

These four bits specify the various color modes:

--------------------------------------------------------
Bits --------------------------------------------------------
7 6 5 4 Color Mode --------------------------------------------------------
               
0     0  x  x  8-bit pseudo color on R7-R0
               
0     1  x  x  8-bit pseudo color on G7-G0
               
1     0  x  x  8-bit pseudo color on B7-B0
               
1     1  0  0  12-bit true color, mode 1 (not used in Leo)
               
1     1  0  1  12-bit true color, mode 2 (not used in Leo)
               
1     1  1  x  24-bit true color

--------------------------------------------------------

10.4.10 Command Register 3

Command register 3 contains eight control bits, as shown in Figure 10-8. Command register 3 is a ten-bit register but only eight bits are used.

    Figure 10-8 RAMDAC Command Register 3 Format

10.4.10.1 Output Clock Frequency

These two bits specify the output frequency of the PRGCKOUT output (not used):

    00 = Clock 4
    01 = Clock 8
    10 = Clock 16
    11 = Clock 32

PRGCKOUT is a divided-down version of the pixel clock.

10.4.10.2 Extra Blank Pipeline Delay Control

These four bits specify the additional pipeline delay that can be added to the blank function, relative to the overall RAMDAC pipeline delay. As the blank control normally enters the RAMDAC from a shorter pipeline than the video pixel data (not true for Leo), this control is useful for de-skewing the pipeline differential. The delay control bits are as follows:

---------------------------------
Bits ---------------------------------
5 4 3 2 Blank Pipeline Delay ---------------------------------
               
0     0  0  0  tPD
               
0     0  0  1  tPD + 1 \xb4 LD_OUT
               
0     0  1  0  tPD + 2 \xb4 LD_OUT
               
.     .  .  .  .
               
.     .  .  .  .
               
1     1  1  1  tPD + 15 \xb4 LD_OUT

---------------------------------

10.4.10.3 Pixel Multiplexer Control

These two bits specify the RAMDAC's multiplex mode. It also determines the frequency of the LD_OUT signal, which is a divided down version of the pixel clock. The pixel multiplexer control bits are as follows:

----------------------------------------------------------
Bits ----------------------------------------------------------
7 6 Blank Pipeline Delay ----------------------------------------------------------
         
0     0  1:1 multiplexing: LD_OUT = CLOCK  1 (not used)
         
0     1  2:1 multiplexing: LD_OUT = CLOCK  2
         
1     0  Reserved
         
1     1  Reserved

----------------------------------------------------------

10.4.11 Mode Register

The mode register is 10 bits wide. However, for programming purposes, it can be thought of as an eight-bit register; bits 8 and 9 are reserved. The mode register is formatted is shown in Figure 10-9.

    Figure 10-9 RAMDAC Mode Register Format

10.4.11.1 Reset Control

The reset control bit resets the pixel port sampling sequence. This ensures that the pixel sequence ABCD starts at A. It is reset by writing a 1, then a 0, then a 1.

10.4.11.2 Resolution Control

The resolution control bit defines the color palette RAM depth:

    0 = 24 bits deep (8 bits each for red, green, and blue)
    1 = 30 bits deep (10 bits each for red, green, and blue)

10.4.11.3 CX Bus Data Width

The CX Bus data width bit determines the width (8 bits or 10 bits) of the CX Bus interface:

    0 = 8 bit
    1 = 10 bit (not used)

10.4.11.4 Operational Mode Control

The operational mode control bits define normal operation or diagnostic test operation:

    0 = Normal mode
    1 = Fast trigger test mode (R7)
    2 = RAM fast-port test mode
    3 = DAC test mode

10.4.11.5 Palette Select Match Bits Control

The palette select match bits allow multiple palette devices to work together. For Leo, these bits are normally set to 11.

    Bit 17 = PS1
    Bit 16 = PS0

10.5 Diagnostic Modes

The RAMDAC allows diagnostic software to debug both the device itself and the device interface to other components in the system. The video or pixel path through the RAMDAC can be monitored through the CX Bus interface. Monitoring points, in the form of test registers, are positioned at the pixel port (LeoCross interface), RAM (color palette tables), and DAC port (video output), as shown in Figure 10-10.

    Figure 10-10 RAMDAC Test Registers

The RAMDAC has four test modes. The test modes are determined by the Mode Register and Command Register 2. Data is latched to the various test registers along the video path by either the pixel clock or by using one bit of pixel data as a trigger (R7).

10.5.1 Diagnostic Mode 0

Mode 0 is the normal chip operation mode. In this mode, the test registers are configured as in Figure 10-11. Both the pixel test register and the DAC test register are triggered every clock cycle. This is operationally transparent. This mode is useful when there is independent control over the clock. By stopping the clock in the low state, the data in the test registers can be read out and verified.

    Figure 10-11 Diagnostic Test Register, Input from Pixel Data Path

10.5.2 Diagnostic Mode 1

Mode 1 is the pixel data path trigger mode. In this mode, the test register trigger is activated by a transition on the R7 bit (bit 7 of the red pixel data) of the pixel port, Figure 10-11. Bit 0 of Command register 2 controls whether the trigger is activated by a rising edge or a falling edge of R7.

The trigger bit is piped through the chip along with the pixel data. This means that each test register captures the pixel with the transition on R7 as it is piped through the chip. Once the data has been captured, it can be read out at any time, even if the pattern is cyclical with the same pixel data repeatedly activating the trigger.

10.5.3 Diagnostic Mode 2

Mode 2 is the RAM fast-port test. In this modem the pixel test register is configured as in Figure 10-11, and the DAC test register is configured as in Figure 10-12.

    Figure 10-12 Diagnostic Test Register, Input from CX Bus Port

10.5.4 Diagnostic Mode 3

Mode 3 is the DAC test. In this mode, the DAC test register and the Sync, Blank, and PLL test register are configured as in Figure 10-12. Data written to the DAC test register and the Sync, Blank, and PLL test register is reflected at the DAC outputs. This allows the DACs to be tested over the CX Bus interface.