Glossary

Accelerator Port

The data path that renders highly used primitives that the Leo Accelerator is optimized to accelerate. The primitives accelerated include dots, lines, and triangles.

ASIC

Application Specific Integrated Circuit

Alpha Transparency

Alpha transparency blends a fraction of the pixel color being written into the color of the pixel from other objects. It thus provides improved visual results. However, it but requires two passes through the display list. The first pass renders opaque objects with the z-buffer enabled. Then the z-buffer is made read-only. The second pass draws transparent objects using the appropriate blending with z-buffer HLHSR (hidden line and hidden surface removal), but does not write the z-buffer. Only one pass is required if the user organizes posted structure networks such that all opaque objects precede all transparent objects. See Screen-Door Transparency.

BG

Background color.

CDBus

Command-Draw Bus. This is a 16-bit data bus that connects LeoCommand, the LeoFloats, and the LeoDraws. LeoCommand controls all data transfer over the bus. The LeoDraws and LeoFloats send status signals to LeoCommand, which sends commands to these chips.

CFBus

Command-Float Bus. This is a 16-bit data bus that connect input signals from LeoCommand to the LeoFloats.

CLUT

Color Look Up Table.

Cursor, Hardware

The LX chip stores cursor information for up 32 \xb4 32 pixels. Larger cursors can be rendered by software.

CXBus

Command-Cross Bus. This is an 8-bit input/output data bus that connect LeoCommand to LeoCross.

DDA

See Digital Differential Analyzer.

Digital Differential Analyzer

This is an algorithm for calculating pixel positions when rendering lines. Basically, unit steps are taken along the major coordinate and the step value along the minor coordinate is calculated for plotting each succeeding position on the line. The major coordinate is the coordinate that has the largest distance between the end points of the line along that coordinate.

Direct Port

The data path that controls direct access to most Leo devices via the CDBus. It is mainily used by the window system and as a path for loading complex primitives (derived by the host is pixel form) into the Frame Buffer.

Facet Normal

A vector perpendicular to a plannar facet (face) of an object. A facet normal defines the orientation of the facet in space, which is needed for lighting calculations.

Global Registers

Global registers are registers whose values have the same meaning for both State Set 0 and 1.

HSPA

Horizontal Sync Pulse Adjustment register.

HSR

Hidden Surface Removal

LC

See "LeoCommand" chip.

LD

See "LeoDraw" chip.

LF

See "LeoFloat" chip.

LUT

Look Up Table.

LX

See "LeoCross" chip.

LeoCommand Chip

This chip is the controller for all Leo ASICs. It communicates with the Host cpu via the SBus.

LeoCross Chip

This chip takes data from the Frame Buffer, matches WIDs with the correct CLUTs, and generates pixels to a RAMDAC that drives a raster monitor. It is also responsible for generating video timing for supporting various display resolutions. Five interleave circuits are used in parallel on the chip to minimize the pixel clock frequency.

LeoDraw Chip

This chip is the rendering engine that draws dots, line, and triangles into the Frame Buffer. It performs edge walking, span interpolation, and pixel processing.

LeoFloat Chip

This chip is the floating point engine. It performs graphics transformation, clipping, and lighting that produces the necessary information for the LDs to render pixels. Three LFs are used in parallel to increase the floating point performance.

Packet

Graphics data is passed to the Leo Graphics Accelerator in groups of 32-bit words called packets. The packet size, which is specified by the "Input Packet Size" field of the "Vertex Mode Control" register, must be between three and 32 words. There are two types of packets: Vertex Packets and Pass-through Packets.

Pass-through List

One or more Pass-throught Packets. The number of packets in a list is specified by the "Input Packet Field" of the "Vertex Mode Register" register.

Pass-through Packet

A packet that contains a header and data that are transparent to and by-pass packet processing functions.

Screen Door Transparency

Screen-door transparency is faster than alpha transparency, but the display quality is not as good. It allows certain pixels to be overwritten, but leaves other pixels under the area untouched (not overwritten). The fraction of the pixels written is the user's transparency coefficient. Screen-door transparency normally spreads out the pixels of each kind "at random".

SRAM

Static Random Access Memory.

State Set 0

The Leo hardware maintains two State Sets for some registers: State Set 0 and 1. These two state sets support randomly intermixed frame buffer accesses from two sets of processes. State Set 0 is used by unaccelerated (Direct Port) processes. Normally the Host uses State Set 0.

State Set 1

The Leo hardware maintains two State Sets: State Set 0 and 1. These two state sets support randomly intermixed frame buffer accesses from two sets of processes. State Set 1 is used by accelerated (Accelerator Port) processes. Normally the LeoCommand chip uses State Set 1.

VCS

Vertex Control Sequencer.

Vertex

Specifies a dot, one end of a line, or one point of a triangle. A vertex is defined by x, y, and z coordinates; optional red, green, and blue colors; and optional normal components.

Vertex List

One or more Vertex Packets. The number of packets in a list is specified by the "Input Packet Field" of the "Vertex Mode Register" register.

Vertex Normal

A vector perpendicular to the surface of a polygon at the point of the vertex. Vertex normals define the orientation of the vertex in space, which is needed for lighting calculations.

Vertex Packet

A packet that contains vertex data for a graphic primitive. The type of graphic primitive (triangle, vector, or dot) is specified by the "Vertex Type" field of the "Vertex Mode Control" register. A Vertex Packet contains a header and one or more vertices.

VINT OPS

Vertical Interval Operations. These are operations that take place during the vertical blanking interval.

VRAM

Video Random Access Memory.