The LeoCommand Chip registers are separated into Direct Port (State Set 0) and Accelerator Port (State Set 1) registers. Also, the registers in each state set operate in one of two clock domains: the SBus Clock Domain or the Leo Clock Domain. These two clock domains have no meaning for software other than bit 11 of the SBus address, which specifies the clock domain.
The SBus address bits for the LeoCommand register address space are shown below.
A<24 = State Set
<-HangingPara_noSA > 0 Access State Set 0 (address 0x020 0XXX) <-HangingPara_noSA > 1 Access State Set 1 (address 0x120 0XXX)A<11 = Clock Domain
<-HangingPara_noSA > 0 Access Leo Clock Domain registers <-HangingPara_noSA > 1 Access SBus Clock Domain registersThe LeoCommand Chip address map is divided into the following four categories:
State Set 0, SBus Clock Domain (see Table 5-1) - these registers are used for control and status operations.
State Set 1, SBus Clock Domain (see Table 5-2) - these registers are used for DMA control.
State Set 0, Leo Clock Domain (see Table 5-3) - these registers are used for control and status, stencil, and block copy/fill operations.
State Set 1, Leo Clock Domain (see Table 5-4) - these registers are used for the Accelerator Port.
In each of these tables, the locations are listed in order by SBus address. However, the registers are described in this chapter in a functional order. The page column in the Address Map refers to the page where that register is described.
-------------------------------------------------------
Page SBus Address Access Register -------------------------------------------------------
5-6 0x020 0800 R LC Chip Code
5-7 0x020 0804 R SBus Status
5-10 0x020 0808 R/W SBus Interrupt Enable
5-11 0x020 080C R/W First Read Timeout Counter
5-12 0x020 0810 R/W Rerun Counter
5-14 0x020 0820 W Clear Read DMA Done
5-13 0x020 0824 W Clear Write DMA Done
5-15 0x020 0828 W Clear Invalid PTE/PTD
5-15 0x020 082C W Clear DMA Error Acknowledge
5-16 0x020 0830 W Clear Slave Illegal Address
5-16 0x020 0834 W Clear Slave Rerun Timeout
5-12 0x020 0840 W Leo Reset
5-13 0x020 0844 W Clear Leo Reset
5-14 0x020 0848 W DMA Read Pause
-------------------------------------------------------
------------------------------------------------------------------------
Page SBus Address Access Register ------------------------------------------------------------------------
5-21 0x120 0800 R/W Table Walk Root Pointer
5-23 0x120 0804 R/W DMA Read PTE/PTD
5-25 0x120 0808 R/W DMA Write Buffer Start Address
5-23 0x120 080C R/W DMA Write Buffer Size
5-25 0x120 0810 R/W DMA Write Current Buffer Address
5-24 0x120 0814 R/W DMA Write Current Buffer Size, Start DMA
Write
5-24 0x120 0818 R/W DMA Write Current Buffer Size, Do Not Start
DMA
5-26 0x120 081C R/W DMA Write Word Count
5-18 0x120 0820 R/W DMA Configuration
5-20 0x120 0824 R/W DMA Write On/Off
5-72 0x120 0828 W Reset Accelerator Port
5-72 0x120 082C W Clear Accelerator Port Reset
5-17 0x120 1800 R DMA Status
5-19 0x120 1804 R/W DMA Read On/Off
5-22 0x120 1808 R/W DMA Read Word Count, Start DMA Read
5-22 0x120 180C R/W DMA Read Word Count, Do Not Start DMA
5-21 0x120 1810 R/W DMA Read Virtual Address
5-26 0x120 1814 R Read Pick FIFO
------------------------------------------------------------------------
-----------------------------------------------------------------------------
Page SBus Address Access Register -----------------------------------------------------------------------------
5-30 0x020 0000 R/W Leo Domain Interrupt Enable
5-40 0x020 0004 W Clear Blt Done
5-73 0x020 0008 W Clear LeoDraw Semaphore
5-28 0x020 1000 R Leo System Status
5-31 0x020 1004 R/W Frame Buffer Address Space
5-33 0x020 1008 R/W Stencil Mask
5-34 0x020 100C R/W Stencil Transparent Enable
5-34 0x020 1010 R/W LC Block Copy/Fill Direction/Size
5-35 0x020 1014 R/W LC Block Copy Source Address
5-39 0x020 1018 R/W LC Block Copy/Fill Destination Address, do not
start copy or fill
5-36 0x020 101C R/W LC Block Copy Destination Address, start copy
5-38 0x020 1020 R/W LC Block Fill Destination Address, start fill
-----------------------------------------------------------------------------
-----------------------------------------------------------------------
Page SBus Address Access Register -----------------------------------------------------------------------
5-70 0x120 0000 R/W LeoFloat Enable Mask
5-71 0x120 0004 W Trigger LeoFloat Interrupt/Run
5-27 0x120 0008 W Write Pick FIFO
5-51 0x120 1000 R/W Vertex Buffer
5-52 0x120 10C0 R/W Alternate Vertex Tupple 1
5-53 0x120 10CC R/W Alternate Vertex Tupple 2
5-53 0x120 10D8 R/W Alternate Vertex Tupple 3
5-54 0x120 10E4 R/W LeoFloat Dispatch
5-46 0x120 1100 R/W Absolute Bucket Buffer
5-46 0x120 1200 R/W Relative Bucket Buffer
5-47 0x120 1300 R/W Launch Relative Bucket Buffer
5-76 0x120 1400 R Accelerator Port Status
5-73 0x120 1404 W Start Vertex Mode
5-74 0x120 1408 W Start Pass Through Mode
5-74 0x120 140C W Start Context Switch Mode
5-75 0x120 1410 W Exit Vertex, Pass Through, or Context Mode
5-31 0x120 1414 R/W Frame Buffer Address Space
5-33 0x120 1418 R/W Stencil Mask
5-34 0x120 141C R/W Stencil Transparent Enable
5-42 0x120 1420 R/W Vertex Mode Control
5-59 0x120 1424 R/W Pass Through Mode Control
5-57 0x120 1428 R/W Pass Through Header
5-66 0x120 142C R/W Auxiliary Vertex Header
5-67 0x120 1430 R/W XGL Constant
5-57 0x120 1434 R/W Subelement Pick ID
5-61 0x120 143C R/W LC Output Format
5-49 0x120 1440 R/W VCS [0] (VCS Opcode 0-3)
5-49 0x120 1444 R/W VCS [1] (VCS Opcode 4-7)
5-49 0x120 1448 R/W VCS [2] (VCS Opcode 8-11)
5-49 0x120 144C R/W VCS [3] (VCS Opcode 12)
5-48 0x120 1450 R/W Vertex Control Sequencer (VCS) Opcode Count
5-41 0x120 1454 R/W Bucket Buffer State Machine
5-63 0x120 1458 R/W Vertex Buffer State Machine
5-68 0x120 145C R/W Vertex Buffer State Machine Control 1
5-68 0x120 1460 R/W Vertex Buffer State Machine Control 2
5-69 0x120 1464 R/W Vertex Buffer State Machine Control 3
5-70 0x120 1468 R/W Vertex Buffer State Machine Control 4
5-77 0x120 146C R/W Last Float Loaded
-----------------------------------------------------------------------
This sections describes the data formats of the LeoCommand chip registers. These registers are described under the following functional groups:
"Direct Port Control and Status Registers" on page 5-6
"Accelerator Port DMA Control Registers" on page 5-16
"Direct Port Control/Status, Stencil, Block Copy/Fill Registers" on page 5-28
"Vertex Packet Logic" on page 5-40
"Bucket Buffer" on page 5-45
"Vertex Format Logic" on page 5-48
"Vertex Buffer Memory" on page 5-50
"Vertex Output Logic" on page 5-61
"Miscellaneous Registers" on page 5-66
For each register the following information is available:
State Set 0 only - one register mapped to State Set 0.
State Set 1 only - one register mapped to State Set 1.
State Set 0 and 1 - there are two registers with the same format, mapped in
the respective state set.
Normally, bits specified as "undefined" return unknown data for reads and are ignored for writes. However, for strobe locations (which are write only) undefined means "don't care" for writes - reads still return unknown data.
These State Set 0, SBus Clock Domain registers are used for Direct Port control and status operations.
0x020 0800
State Set 0 only; SBus clock; Read only
This is a 32- bit code that identifies the LC chip. It is a read only register and writes to it are acknowledged but ignored.
D<31:28 = Version
Specifies the version of the LeoCommand chip.
D<27:12 = Device Identification
The device identification code for the LeoCommand chip.
D<11:1 = JED Manufacturer Code
The JED manufacturer code assigned to Sun Microsystems or vender.
D<0 = 1
Allways in the high state.
0x020 0804
State Set 0; SBus clock; Read only
Various status signals from the Leo DMA engines and error conditions can be read from this register. Writes to this register are acknowledged but ignored.
D<9 = Leo Reset Status
<-HangingPara_noSA > 0 Leo soft reset not active <-HangingPara_noSA > 1 Leo soft reset is active. This is the soft reset to the Leo system. It is set by accessing the "Leo Reset" strobe address (see page 5-12) and cleared by accessing the "Clear Leo Reset" strobe address (see page 5-13).
D<8 = DMA Read Pause Active
The DMA Read Engine is active only when the DMA Read Pause Active bit is
0 and the Read DMA Busy bit in the "DMA Status" register is 1. While this bit
is off and the Read DMA bit is on, the DMA Read Engine does a table walk to
find the PTE.
D<7 = DMA Read Pause
<-HangingPara_noSA > 0 The DMA Read Pause bit is not active <-HangingPara_noSA > 1 The DMA Read Pause bit is activeD<6 = Acc Port Reset Status
<-HangingPara_noSA > 0 Accelerator port soft reset not active <-HangingPara_noSA > 1 Accelerator port soft reset is active. This is the soft reset to the Accelerator port. It is set by accessing the "Reset Accelerator Port" strobe address (see page 5-72) and cleared by accessing the "Clear Accelerator Port Reset" strobe address (see page 5-72).D<5 = Slave Rerun Timeout
<-HangingPara_noSA > 0 A Slave Rerun Timeout condition has not occurred <-HangingPara_noSA > 1 A Slave Rerun Timeout condition has occurred. Set by SBus slave hardware if a slave access causes more reruns than the value contained in the Rerun Counter (see page 5-12). Cleared by accessing the "Clear Slave Rerun Timeout" strobe address (see page 5-16).D<4 = Slave Illegal Addr
<-HangingPara_noSA > 0 A Slave Illegal Address condition has not occurred <-HangingPara_noSA > 1 A Slave Illegal Address condition has occurred. Set by SBus slave hardware if an illegal address condition has occurred. Cleared by accessing the "Clear Slave Illegal Address" strobe address (see page 5-16). An illegal address condition occurs when an access is made unspecified location in the address map, a write is made to a read only location, or a read is made to a write only location. If this occurs, kill the process.D<3> = DMA Error Ack
<-HangingPara_noSA > 0 A DMA Error Acknowledge has not occurred <-HangingPara_noSA > 1 A DMA Error Acknowledge has occurred. Set by either the Read or Write DMA hardware if an error acknowledgment is received on an SBus transaction. Cleared by accessing the "Clear DMA Error Acknowledge" strobe address (see page 5-15). If this occurs, kill the process.D<2 = Invalid PTE/PTD
<-HangingPara_noSA > 0 An invalid PTE/PTD condition has not occurred <-HangingPara_noSA > 1 An invalid PTE/PTD condition has occurred during Table Walk in the Read DMA. Set by the Read DMA hardware during Table Walk if an invalid PTE/PTD entry is found. The invalid PTE/PTD is held in the "DMA Read PTE/PTD"register (see page 5-23). Cleared by accessing "Clear Invalid PTE/PTD" strobe address (see page 5-15).D<1 = Write DMA Done
<-HangingPara_noSA > 0 Write DMA is not done <-HangingPara_noSA > 1 Write DMA is done. Set by the Write DMA hardware, cleared by accessing "Clear Write DMA Done" strobe address (see page 5-13). The Write DMA hardware sets this bit when the DMA Write Buffer Size amount of data has been DMA'ed (see page 5-23). Note that for a circular buffer, this status bit has no meaning. DMA writes are used for both pick events and SRAM reads. Do not do a pick and a SRAM read at the same time - they get intermingled in the FIFO.D<0 = Read DMA Done
<-HangingPara_noSA > 0 Read DMA is not done <-HangingPara_noSA > 1 Read DMA is done. Set by the RD DMA hardware, cleared by accessing "Clear Read DMA Done" strobe address (see page 5-14). Note that this bit is not set right away because of latency. DMA reads transfer vertex data from the Host System Memory to the Bucket Buffer.
0x020 0808
State Set 0; SBus clock; Read and Write
The interrupt sources can be enabled to interrupt on the SBus using this register. The interrupt conditions are indicated by the bits in the "SBus Status" register (see page 5-7).
D<6 = Pick Fifo Not Empty Int Enb
<-HangingPara_noSA > 0 Disable interrupt for Pick Fifo Not Empty <-HangingPara_noSA > 1 Enable interrupt for Pick Fifo Not Empty.D<5 = Slave Rerun Timeout Int Enb
<-HangingPara_noSA > 0 Disable interrupt for Slave Rerun Timeout <-HangingPara_noSA > 1 Enable interrupt for Slave Rerun Timeout. The Slave Rerun Timeout bit in the SBus Status register indicates the interrupt condition.D<4 = Slave Illegal Addr Int Enb
<-HangingPara_noSA > 0 Disable interrupt for Slave Illegal Address <-HangingPara_noSA > 1 Enable interrupt for Slave Illegal Address. The Slave Illegal Address bit in the SBus Status register indicates the interrupt condition.D<5 = DMA Error Ack Int Enb
<-HangingPara_noSA > 0 Disable interrupt for DMA Error Acknowledge <-HangingPara_noSA > 1 Enable interrupt for DMA Error Acknowledge. The DMA Error Acknowledge bit in the SBus Status register indicates the interrupt condition.D<2 = Invalid PTE/PTD Int Enb
<-HangingPara_noSA > 0 Disable interrupt for Invalid PTE/PTD. <-HangingPara_noSA > 1 Enable interrupt for Invalid PTE/PTD. The Invalid PTE/PTD bit in the SBus Status register indicates the interrupt condition.D<1 = Write DMA Done Int Enb
<-HangingPara_noSA > 0 Disable interrupt for Write DMA Done. <-HangingPara_noSA > 1 Enable interrupt for Write DMA Done. The Write DMA Done bit in the SBus Status register indicates the interrupt condition.D<0 = Read DMA Done Int Enb
<-HangingPara_noSA > 0 Disable interrupt for Read DMA Done. <-HangingPara_noSA > 1 Enable interrupt for Read DMA Done. The Read DMA Done bit in the SBus Status register indicates the interrupt condition.
0x020 080C
State Set 0; SBus clock; Read and Write
This register counts down for each SBus clock from a preset value when a read request is decoded in the SBus. If data is not yet available when this counter reaches zero, LeoCommand issues a rerun. This counter affects only the first read request. Subsequent read request of the same address are issued a rerun immediately until data becomes available.
The default value of this register is 20.
0x020 0810
State Set 0; SBus clock; Read and Write
The value of this register determines the number of reruns Leo can generate when accessed as an SBus slave. The Slave Rerun Timeout bit in the "SBus Status" register (see page 5-7) is set if the number of reruns exceeds that count.
For an SBus slave write, Leo issues an immediate acknowledgment and places the write command in the FIFO. For an SBus slave read, Leo places the read command in the FIFO. If there isn't any room in the FIFO for an SBus read or write command, Leo issues a rerun. If the read command is in the FIFO and the data does not return within approximately 240 cycles, Leo issues a rerun on the SBus. This will rarely occur.
0x020 0840
State Set 0; SBus clock; Write only (Strobe)
Writing to this location resets the Leo system; it is the Leo soft reset. It clears everything but some of the controllers, the slave read/write registers, and the SBus states. The reset signal stays active until it is inactivated by the Clear Leo Reset strobe. The reset condition can be read as status in the Leo Reset Status bit of the SBus Status Register (see page 5-7). This is a "strobe" location - the data is a "don't care."
0x020 0844
State Set 0; SBus clock; Write only (Strobe)
Writing to this location deactivates the reset condition in the Leo system. If the reset condition was not active, nothing happens. The software must not write to this location for at least 1 microseconds after doing a Leo Reset. This is a "strobe" location - the data is a "don't care."
0x020 0824
State Set 0; SBus clock; Write only (Strobe)
Writing to this location clears the Write DMA Done bit in the SBus Status Register. This is a "strobe" location - the data is a "don't care."
0x020 0820
State Set 0; SBus clock; Write only (Strobe)
Writing to this location clears the Read DMA Done bit in the SBus Status Register. This is a "strobe" location - the data is a "don't care."
0x020 0848
State Set 0; SBus clock; Write only
Writing to a 1 to this location causes the DMA Read Engine to pause. Writing a 0 stops the pause.
0x120 0828
State Set 0; SBus clock; Write (Strobe)
Writing to this location clears the Invalid PTE/PTD bit in the SBus Status Register. This is a "strobe" location - the data is a "don't care."
0x120 082C
State Set 0; SBus clock; Write (Strobe)
Writing to this location clears the DMA Error Acknowledge bit in the SBus Status Register. This is a "strobe" location - the data is a "don't care."
0x120 0830
State Set 0; SBus clock; Write (Strobe)
Writing to this location clears the Slave Illegal Address bit in the SBus Status Register. This is a "strobe" location - the data is a "don't care."
0x120 0834
State Set 0; SBus clock; Write (Strobe)
Writing to this location clears the Slave Rerun Timeout bit in the SBus Status Register. This is a "strobe" location - the data is a "don't care."
These State Set 1, SBus Clock Domain registers are used for Accelerator Port DMA control.
0x120 1800
State Set 1 only; SBus clock; Read only
Status signals from the Leo DMA engines are available in this register.
D<4 = Pick FIFO Empty
The Pick FIFO is used to hold both pick data and SRAM read data.
D<3 = Write DMA Busy
This is a shadow copy of the Write DMA On status bit, but is a delayed version
by some number of hardware clocks. The status of this flag is the real
indication that the DMA Write hardware is idle.
D<2 = Read DMA Busy
This is a shadow copy of the Read DMA On status bit, but is a delayed version
by some number of hardware clocks. The status of this flag is the real
indication that the DMA Read hardware is idle.
D<1 = Write DMA On
Indicates Write DMA Status. Set to 1 by writing a 1 to the "DMA Write
On/Off" register (see page 5-20) or by writing a nonzero value into the "DMA
Write Current Buffer Size, Start DMA Write" register. Cleared to 0 by writing a
0 to the DMA Write On/Off register or by the DMA Write hardware when the
DMA Write Current Buffer Size register goes to zero.
D<0 = Read DMA On
Indicates Read DMA Status. Set to 1 by writing a 1 to the "DMA Read On/Off"
register (see page 5-19) or by writing a nonzero value into the "DMA Read
Word Count, Start DMA Read" register (see page 5-22). Cleared to 0 by writing
a 0 to the "DMA Read On/Off" register or by the DMA Read hardware when
the DMA Read Word Count register goes to zero.
0x120 0820
State Set 1 only; SBus clock; Read and Write
The SBus size (32 or 64 bits), the burst size used for DMA Read operations, and the circular or linear buffer operation of the DMA Read operation are programmed in this register. Note that the SBus Size/Burst Mode field only applies to the DMA Read operations, not to DMA Write. DMA Write operations always use 32-bit SBus and one word burst.
D<31:25 = DMA Read SBus Size/Burst Mode
This 7-bit field is coded as follows:
D<24 = Circular Or Linear Mode
<-HangingPara_noSA > 0 DMA Write buffer is treated as a linear buffer <-HangingPara_noSA > 1 DMA Write buffer is treated as a circular buffer
0x120 1804
State Set 1 only; SBus clock; Write only
This register controls the start and stop of the DMA Read operation. The DMA Read hardware takes data from host memory and DMAs it into the Bucket Buffer in the LeoCommand Accelerator Port. To check the result of writing to this register, read the Read DMA Busy bit of the DMA Status register (see page 5-17).
The DMA hardware clears this bit at the end of the DMA.
D<0 = DMA Read On
<-HangingPara_noSA > 0 Stop DMA Read operation <-HangingPara_noSA > 1 Start DMA Read operation
0x120 0824
State Set 1 only; SBus clock; Write only
This register controls the start and stop of the DMA Write operation. To check the result of writing to this register, read the Write DMA Busy bit of the DMA Status register (see page 5-17).
The DMA Write hardware DMAs the contents of the Pick FIFO in the LeoCommand chip into a buffer in host memory. The starting address of this buffer is specified in the "DMA Write Current Buffer Address" register (see page 5-25) and the size of the buffer is specified in the DMA Write Current Buffer Size register (see page 5-24).
As the DMA progresses, the hardware increments the current address and decrements the current size. When the size count reaches zero, the hardware sets the DMA Write Done status bit in the DMA Status register. In many applications, this is the end of the DMA Write operation.
However, if the Circular or Linear Mode bit in the DMA Configuration register (see page 5-18) indicates a circular buffer, the DMA Write operation continues after the DMA Write Buffer Size is loaded into the DMA Write Current Size register and the DMA Write Start Address is loaded into the DMA Write Current Buffer Address register. This in effect resets the address to the beginning of the DMA Write buffer and allows the transfer of another Buffer Size of DMA. For the circular buffer case, the DMA goes on until the software stops loading data into the Pick FIFO.
D<0 = DMA Write On
<-HangingPara_noSA > 0 Stop DMA Write operation <-HangingPara_noSA > 1 Start DMA Write operation
0x120 0800
State Set 1 only; SBus clock; Read and Write
This register contains the address of the level - 1 page table used for Table Walk by the Read DMA hardware. It is loaded by the device driver.
0x120 1810
State Set 1 only; SBus clock; Read and Write
The application loads the starting virtual address for the Read DMA into this register. During DMA, this address is incremented.
0x120 1808
State Set 1 only; SBus clock; Read and Write
This register contains the size of the data to be transferred through DMA Read hardware. The value is the total number of words to DMA and may span several pages of data. If the DMA does span more than a page, the DMA Read hardware does a Table Walk between each page.
This register address also starts the DMA Read hardware, which is indicated in the Read DMA Busy bit in the DMA Status Register. The hardware decrements the value in the DMA Read Word Count register as the DMA progresses. When the value reaches zero, the hardware sets the Read DMA Off status bit in the SBus Status register and then clears the Read DMA Busy status bit in the DMA Status register.
0x120 180C
State Set 1 only; SBus clock; Read and Write
This is the same register as accessed at address 0x120 0908 (holds the DMA Read Word Count), but the DMA Read hardware does not start when this address is accessed.
0x120 0804
State Set 1 only; SBus clock; Read and Write
This register contains the PTD (Page Table Descriptor) or the PTE (Page Table Entry) resulting from the Table Walk. It's contents change as the Table Walk progresses.
0x120 080C
State Set 1 only; SBus clock; Read and Write
Used only for a circular buffer. When the hardware reaches the end of the buffer, it write the contents of the this register into the DMA Write Current Buffer Size register.
0x120 0814
State Set 1 only; SBus clock; Read and Write
Load this register with the word size of the host memory buffer that you want DMA data written to. As DMA progresses, the hardware decrements the contents of this register. When the count reaches zero, the Write DMA On bit in the SBus Status register is cleared and then the Write DMA Busy bit in the DMA Status register is cleared. For a circular buffer, when hardware reaches the end of the buffer, it write the contents of the "DMA Write Buffer Size" register into this register.
0x120 0818
State Set 1 only; SBus clock; Read and Write
This is the same register as above (holds the DMA Write Current Buffer Size),
but, the DMA Write hardware is not started when this location is accessed. The
"DMA Write On/Off" register is used to start the DMA write.
0x120 0808
State Set 1 only; SBus clock; Read and Write
Used only for a circular buffer. When the hardware reaches the end of the buffer, it write the contents of the this register into the "DMA Write Current Buffer Address" register.
0x120 0810
State Set 1 only; SBus clock; Read and Write
Load this register with the starting address of the host memory buffer where you want DMA data written. The DMA hardware uses the contents of this register for the address to DMA to. As DMA progresses, the hardware increments the contents. For a circular buffer, when the hardware reaches the end of the buffer, it writes the contents of the "DMA Write Buffer Start Address" into this register.
0x120 081C
State Set 1 only; SBus clock; Read and Write
The DMA Write hardware increments the contents of this register for every write to the DMA Write Buffer, in effect, indicating the number of bytes DMA'ed. The device driver should clear this register to zero to get meaningful count data.
0x120 1814
State Set 1 only; SBus clock; Read only
The LeoCommand pick control hardware reads the Pick IDs from the LeoDraw chips and writes this data into the Pick FIFO. The pick data can then be DMA'ed or read out using programmed I/O. For DMA Write operations, the DMA Write hardware reads the Pick FIFO and DMAs its contents into a buffer in host memory.
The Pick FIFO is also the memory used to store data sent from LeoFloats for things like SRAM reads. After the LeoFloats receive a packet over the Accelerator Port to output some data, they signal LeoCommand that they have data. This data is then put into the Pick FIFO. The data the LeoFloats put into the Pick FIFO can also be DMA'ed out or read through programmed I/O. The Pick FIFO Empty bit in the DMA Status Register indicates if there is data in the Pick FIFO.
The downloader and XGL can use programmed I/O to read this register.
0x120 0008
State Set 1 only; SBus clock; Write only
This register allows the software to write to the Pick FIFO. It should only be used by the kernel and diagnostics. In normal operation, the LeoCommand pick control hardware reads the Pick IDs from the LeoDraw chips and writes this data into the Pick FIFO. The pick data can then be DMA'ed or read out of the "Read Pick FIFO" register (see page 5-26) using programmed I/O. For DMA Write operations, the DMA Write hardware reads the Pick FIFO and DMAs its contents into a buffer in host memory.
These State Set 0, Leo Clock Domain registers are used for Direct Port control and status, stencil, and block copy/fill operations.
0x020 1000
State Set 0 only; Leo clock; Read only
Various signals from the CDBus, CFBus, and CXBus are available as read only status in this register for diagnostics purposes. Writes to the register are acknowledged but no action occurs. The CFBus CF Buf Avl signals can be used to indicate the number of LeoFloat ASIC's in the system. After reset, the LeoFloat's that are in the system indicate that their buffers are available and the other status signals indicate that the buffers are not available.
D<31 = LeoDraw Semaphore
This bit is set if any of the LeoDraw semaphore bits (or BLT Done for O'Keefe)
are set when a LeoDraw interrupt is received. It is cleared by a strobe write to
address 0x020 0008.
D<30 = BLT Done
This bit is set by the Blt hardware when the Block Copy/Fill is complete. It is
cleared by writing to the "Clear Blt Done" register.
D<29 = BLT Busy
<-HangingPara_noSA > 0 The Block Copy/Fill Controller is not active <-HangingPara_noSA > 1 The Block Copy/Fill Controller is busy
D<28 = Scoreboard Empty
The scoreboard is the logic that keeps track of the data packets sent to and
output from the LeoFloats on the Accelerator Port. An empty flag indicates
that all primitive packets sent to LeoFloats have been processed and sent to
LeoDraws and that the LeoFloats are waiting for data.
D<27 = CXBus Vert Int
Indicates an interrupt from a LeoCross chip to the LeoCommand chip on. This
bit is reset by accessing the LeoCross chip.
D<26:23 = CFBus CF Buf Avl
LeoFloat buffer available status to LeoCommand on the cf_buf_avl<3:0 lines.
D<22:21 = CDBus Flt3 Status
LeoFloat 3 status to LeoCommand.
D<20:19 = CDBus Flt2 Status
LeoFloat 2 status to LeoCommand.
D<18:17 = CDBus Flt1 Status
LeoFloat 1 status to LeoCommand.
D<16:15 = CDBus Flt0 Status
LeoFloat 0 status to LeoCommand.
D<14:10 = CDBus Draw Intrpt
Indicates an interrupt signal from a LeoDraw chip to the LeoCommand chip.
These bits are reset by accessing the LeoDraw chips.
D<9:5 = CDBus Dir Buf Avl
Direct Port buffer available signals from the LeoDraw chip to the
LeoCommand chip.
D<4:0 = CDBus Acc Buf Avl
Accelerator Port buffer available signals from the LeoDraw chip to the
LeoCommand chip.
0x020 0000
State Set 0 only; Leo clock; Read and Write
The interrupt sources in the Leo clock domain can be enabled to interrupt on the SBus using this register.
D<4 = Semaphore Intrpt Enable
The LeoDraw Semaphore status bit in the "Leo System Status" register (see
page 5-28) indicates the interrupt condition.
D<3 = BLT Done Intrpt Enable
The Blt Done status bit in the "Leo System Status" register (see page 5-28)
indicates the interrupt condition.
D<2 = Scoreboard Empty Intrpt Enable
Interrupts when the scoreboard is empty. The Scoreboard empty field in the
"Leo System Status" register indicates the interrupt condition. This
information is used by the device driver to tell when to do a context switch.
Note that if data packets are being sent on the Accelerator Port with the interrupt enabled, the scoreboard may empty causing an interrupt, but when the interrupt is serviced the scoreboard may no longer be empty. Data to the Accelerator Port should be stopped before enabling this interrupt.
<-HangingPara > 0 Disable interrupt from scoreboard <-HangingPara_noSA > 1 Enable interrupt from scoreboard
D<1 = LX Int Enable
The CXBus Cxint field in the "Leo System Status" register indicates the
interrupt condition.
D<0 = LD Int Enable
The CDBus Draw Intrpt field in the "Leo System Status" register indicates the
interrupt condition.
0x020 1004 for State Set 0
0x120 1414 for State Set 1
State Set 0 and 1; Leo clock; Read and Write
The contents of this register are used for determining the memory partition to be used for Frame Buffer accesses.
D<3:0 = Access Code
The Access Code is coded as shown in Table 5-5. As shown in the table, Pixel
Access Mode only supports 4-byte accesses, while the Stencil and Byte Access
Modes support 1-byte, 2-byte, and 4-byte access. If an illegal access is done, the
SBus transaction is completed, however, the results are not specified and the
Slave Illegal Address bit in the SBus Status register (see page 5-7) is set.
----------------------------------------------
Code Access Plane 4-Byte 2-Byte 1-Byte Mode Group Access Access Access ----------------------------------------------
0000 Pixel Image OBGR Illegal Illegal
0001 Pixel Depth Z Illegal Illegal
0010 Pixel Window W Illegal Illegal
0011 Pixel Illegal Illegal Illegal Illegal
0100 Stencil Image SSSS SSxx Sxxx
0101 Stencil Depth SSSS SSxx Sxxx
0110 Stencil Window SSSS SSxx Sxxx
0111 Stencil Unused Illegal Illegal Illegal
1000 Byte Image-O OOOO OOxx Oxxx
1001 Byte Image-B BBBB BBxx Bxxx
1010 Byte Image-G GGGG GGxx Gxxx
1011 Byte Image-R RRRR RRxx Rxxx
11xx Unused Illegal Illegal Illegal
----------------------------------------------
0x020 1008 for State Set 0
0x120 1418 for State Set 1
State Set 0 and 1; Leo clock; Read and Write
The Stencil Mask is used to mask off pixels when using stencil mode access. For each bit in the stencil mask, a 1 enables writes and 0 disables writes to the corresponding pixel. Bit 31 represents the leftmost pixel on the display. Mask bits 31 - 24 are used for byte stencil accesses, bits 31 - 16 are used for 2-byte stencil accesses, and bits 31 - 00 are used for 4-byte stencil accesses. The Stencil Mask data formats are shown in Figure 5-1.
Figure 5-1 Stencil Mask Data Formats
0x020 100C for State Set 0
0x120 141C for State Set 1
State Set 0 and 1; Leo clock; Read and Write
Specifies whether stencil's are opaque or transparent during a Stencil Mode access. For opaque stencils, the background (stencil bit = 0) or foreground (stencil bit = 1) color value is written to the Frame Buffer for each bit location. For transparent stencils, the pixels whose stencil bits = 0 are left unchanged (transparent).
D<0 = Stencil Transparent Enable
<-HangingPara_noSA > 0 Opaque stencil, write background pixels with background color <-HangingPara_noSA > 1 Transparent stencil, don't modify background pixels
0x020 1010
State Set 0 only; Leo clock; Read and Write
Specifies the size of a rectangle copy or fill operation, and the direction for a copy operation.
D<31 = Block Copy Direction
The copy direction is important when the source rectangle overlaps the
destination rectangle. Choose the copy direction so that source pixels are not
overwritten before they are copied.
D<20:11 = Block Copy Height
Height of the rectangle in number of scan lines.
D <10:0 = Block Copy Width
Width of the rectangle in number of pixels.
0x020 1014
State Set 0 only; Leo clock; Read and Write
Specifies the address of the source rectangle and the source memory buffer for a rectangle block copy operation.
D<31:30 = Source Select
Selects the source buffer for the block copy. The Mode bit (M) from the Block
Copy Destination Address is used in conjunction with this field (SS) to
determine the source buffer. The Mode bit determines whether 32-bit or 8-bit
copies are being done. The encoding of the Mode and the Source Select bits is:
D<21:11 = Source Y Address
Specifies the source Y address.
D<10:0 = Source X Address
Specifies the source X address.
0x020 101C
State Set 0 only; Leo clock; Read and Write
Specifies the address of the destination rectangle for block copy. The destination memory buffer is selected through the Destination Select bits (DD) for 32-bit copies. When an 8-bit copy is selected through the Mode bit (M), the Image Write Mask in the LeoDraw chips select the destination buffer and the DD bits are ignored. Writing to this address triggers the block copy; do not write to this address until all other block copy operation registers are set up properly. Reading this address after a copy returns the last destination address - the last X and last Y.
The LeoCommand chip does not block access on the SBus slave port when the block copy is active. An access on any state to any location interrupts the block copy for that access. The copy stops for the few cycles required to do the access, then continues.
Shapes code must check that a block copy is complete before doing any other operation that touches video ram. This includes not releasing the window lock to DGA. Check that the Blt Busy bit in the "Leo System Status" register (see page 5-28) equals zero.
D<31 = Mode
The Mode bit (M) is used in conjunction with the Destination Select bits (DD)
to determine the destination buffer. The Mode bit determines whether 32-bit or
8-bit copies are being done.
D<31:30 = Destination Select
Selects the destination buffer for a block copy operation. The encoding of the
Mode and the Destination Select bits is:
D<20:11 = Destination Y Address
Specifies the destination Y address.
D<10:0 = Destination X Address
Specifies the destination X address.
0x020 1020
State Set 0 only; Leo clock; Read and Write
Selects the address of the destination rectangle for block fill. The destination memory buffer is selected through the Destination Select bits (DD) for 32-bit fills. When an 8-bit fill is selected through the Mode bit (M), the Image Write Mask in the LeoDraw chips select the destination buffer and the DD bits are ignored. Writing to this address triggers the block fill; do not write to this address until all other fill operation registers are set up properly. Reading this address after a fill operation returns the last destination address - the last X and last Y.
D<31 = Mode
The Mode bit (M) is used in conjunction with the Destination Select bits (DD)
to determine the destination buffer. The Mode bit determines whether 32-bit or
8-bit copies are being done.
D<31:30 = Destination Select
Selects the destination buffer for a fill operation. The encoding of the Mode and
the Destination Select bits is:
D<20:11 = Destination Y Address
Specifies the destination Y address.
D<10:0 = Destination X Address
Specifies the destination X address.
0x020 1018
State Set 0 only; Leo clock; Read and Write
Selects the address of the destination rectangle for block copy or fill. The destination memory buffer is selected through the Destination Select bits (DD) for 32-bit fills. When an 8-bit fill is selected through the Mode bit (M), the Image Write Mask in the LeoDraw chips select the destination buffer and the DD bits are ignored. Writing to this address does not triggers the block copy or fill. Reading this address after a copy or fill operation returns the last destination address - the last X and last Y.
D<31 = Mode
The Mode bit (M) is used in conjunction with the Destination Select bits (DD)
to determine the destination buffer. The Mode bit determines whether 32-bit or
8-bit copies or fills are being done.
D<31:30 = DESTINATION SELECT
Selects the destination buffer for a copy or fill operation. The encoding of the
Mode and the Destination Select bits is:
D<20:11 = Destination Y Address
Specifies the destination Y address.
D<10:0 = Destination X Address
Specifies the destination X address.
0x020 0004
State Set 0 only; Leo clock; Write only (Strobe)
Writing to this location clears the Blt Done status bit in the "Leo System Status" register. This is a "strobe" location - the data is a "don't care."
These State Set 1, Leo Clock Domain registers control the Vertex Packet Logic. The Vertex Packet Logic consists of the "Bucket Buffer State Machine" register and the "Vertex Mode Control" register.
0x120 1454
State Set 1 only; Leo clock; Read and Write
The Bucket Buffer State Machine is the logic in the Leo Clock Domain that controls transfers in and out of the Bucket Buffer. For context switches, the state of this state machine and associated parameters must be saved and restored to ensure proper operation. This register holds that state. Other than saving and restoring the context, software normally does not read or write this register.
D<29:26 = Port Mode
Specifies the interim state of the Bucket Buffer controllers for input loading and
pointer control. Context idle states are limited to a small number of states. The
port mode flags define the DMA/Immediate and Pass-Through/Vertex modes
of operation, which are auto-started after a context switch.
D<25:22 = Bucket Buffer Ctrl
Bucket Buffer control context states are: 0x0 or 0x1 dependent on DMA and
empty/partial packet state.
D<12:8 = Partl Pkt Base Addr
Specifies the base address (ba) of partial packet or first word address. ba = 0 for
the first packet.
D<5:0 = Word Rel Ptr
Specifies the interim word address of a partial packet. The address is relative to
the base address. This field is used by DMA mode only.
0x120 1420
State Set 1 only; Leo clock; Read and Write
These fields affect how the LeoCommand chip prepares vertex packets for the LeoFloat chips. The Vertex Type field specifies whether the primitive is a triangle (three vertices per LeoFloat packet), vector (two vertices per LeoFloat packet) or dot (one vertex per LeoFloat packet). The Vertex Format field specifies the source tupple count. The hardware assembles the source tupple, perhaps inserts facet tupples, perhaps substitutes alternate tupples, and formats the values. The example below shows the generic format for a triangle that the hardware forwards to the LeoFloat chips:
<-ParaIndent1_tab > LeoFloat Dispatchwhere:
<-HangingParaIn1_noSA > VP Vertex Position <-HangingParaIn1_noSA > VN Vertex Normal <-HangingParaIn1_noSA > VC Vertex Color <-HangingParaIn1_noSA > FN Facet NormalThe First, Second, and Third Vertices in this context are just the three vertices of the current triangle and do not correspond to the vertex buffer locations. The Header Source Vertex is selected by the Header Source field.
Bits 7 through 2 of the "Pass Through Mode Control" register (see page 5-59) are also used during Vertex Mode.
D<18 = Subelement PID Count with Header
Code with bits 7:5.
D<17 = Header Source
<-HangingPara_noSA > 0 Use header from newest vertex; also use Pick ID, replicate from, and get tupple 3 from newest. <-HangingPara > 1 Use header from oldest vertex; also use Pick ID, replicate from, and get tupple 3 from oldest.
D<16:12 = Input Packet Size
The input packet size must be at least three words due to pipeline lookahead.
If only one word is needed, the software may only load one of these three
words.
D<11 = Vertex DMA Mode
This bit selects the DMA Mode or Immediate Mode of operation when Vertex
Mode is set by accessing the "Start Vertex Mode" register (see page 5-73).
D<10 = Polyline Mode
This field specifies whether to treat each vertex pair as a separate vector.
(Create vectors between V1,V2 and V3,V4 but not between V2,V3). This bit
applies only when the Vertex Type = vector.
D<9 = Edge Mode Enable
<-HangingPara_noSA > 0 Edge Mode inactive <-HangingPara_noSA > 1 Edge Mode enabled
D<8 = Backface Function
Set this bit to reverse the normal triangle vertex ordering. It reverses the
Counterclockwise bit in the header and reverses the order of vertex 1 and
vertex 2 in the output primitives. This bit applies only when the Vertex Type =
triangle.
The Backface Function bit works as follows. The header of the first triangle of a strip contains the Counter ClockWise (CCW) bit, which specifies the ordering of triangle vertices sent to LeoFloat. This bit affects the remainder of the triangle strip. The first triangle of the strip is sent out based on the initial setting. Any subsequent triangle formed by replacing the middle vertex (V2), retains the same vertex ordering. A triangle formed by replacing the oldest vertex (V1) reverses the triangle vertex ordering. A restart is the same as starting a new strip in that it loads the CCW bit again.
<-HangingPara > 0 Send triangle vertices in the order specified by the current setting of the internal CCW bit <-HangingPara_noSA > 1 Send triangle vertices in the opposite order as that specified by the current setting of the internal CCW bit
D<7:5 = Subelement Pick ID Control
This field specifies whether to include Pick ID information after the header half
word, and how to increment the value. The Pick ID information can come from
the vertex header or from the "Subelement Pick ID" register (see page 5-57). Bit
18 (Subelement PID Count with Header) is coded with these three bits as
follows:
D<4 = Facet Normal Enable
This bit specifies whether to append the facet value (typically a Facet Normal)
after the last vertex.
D<3:2 = Vertex Format
<-HangingPara_noSA > 00 XYZ + Tupple 1 + Tupple 2 <-HangingPara_noSA > 01 XYZ + Tupple 1 <-HangingPara_noSA > 1x XYZD<1:0 = Vertex Type
<-HangingPara_noSA > 00 reserved <-HangingPara_noSA > 01 Dot <-HangingPara_noSA > 10 Vector <-HangingPara_noSA > 11 TriangleThese State Set 1, Leo Clock Domain registers control the Bucket Buffer. There are three bucket buffers: the Absolute Bucket Buffer, Relative Bucket Buffer, and Launch Relative Bucket Buffer.
0x120 1100 thru 0x120 117F (32 words; 128 bytes)
State Set 1 only; Leo clock; Read and Write
The Bucket Buffer is a 32-word memory block through which all data into the Accelerator Port passes. It can be written and read by programmed I/O (immediate mode) or written to by the DMA engine. This location is the absolute address access of the bucket buffer. It is used only for context switching and for diagnostics.
0x120 1200 thru 0x120 127F (32 words; 128 bytes)
Base Address thru Base Address + Packet Size - 1
State Set 1 only; Leo clock; Read and Write
This is the relative address access part of the Bucket Buffer used by immediate mode accesses. The access is relative to a packet base specified by the hardware. The software only needs to set the size of input packet using the "Vertex Mode Control" register (see page 5-42). The hardware automatically sets all the pointers. The software writes each word of a packet, except the last word, to this buffer. The software writes the last word in a packet to the Launch Relative Bucket Buffer to launch the packet.
0x120 1300 thru 0x120 137F (32 words; 128 bytes)
Base Address thru Base Address + Packet Size - 1
State Set 1 only; Leo clock; Read and Write
Same as the Relative Bucket Buffer except that an access into this address space launches the vertex packet (marks the vertex as complete during immediate mode access of the Accelerator Port allowing the hardware to process it). This also causes the hardware to change the packet base address, and to get the bucket ready for the next packet. This register requires a few cycles before it will accept another write. Any other SBus activity between writes to this register is longer than this period.
There are two ways to tell if there is enough room to write another packet to the Bucket Buffer. The first way is to check bit 9 (Bucket Buffer Space Available Status) of the "Accelerator Port Status" register (see page 5-76) to see if there is enough space for the next packet. The size of the next packet is specified in bits 16 through 12 of the "Vertex Mode Control" register. The second way is to check bits 4 through 0 (Bucker Buffer Words Available) of the "Accelerator Port Status" register to see how many packets may be written.
These State Set 1, Leo Clock Domain registers control the Vertex Format Logic. The Vertex Format Logic consists of the Vertex Control Sequencer (VCS) Opcode Count register and a four-word block of memory (VCS Opcode registers) containing up to 13 opcodes (VCS OP[0] through VCS OP[12]).
0x120 1450
State Set 1 only; Leo clock; Read and Write
This value determines the number of VCS (Vertex Control Sequencer) Opcodes that are executed during the processing of vertex data.
0x120 1440 for VCS [0] (VCS Opcode 0-3)
0x120 1444 for VCS [1] (VCS Opcode 4-7)
0x120 1448 for VCS [2] (VCS Opcode 8-11)
0x120 144C for VCS [3] (VCS Opcode 12)
State Set 1 only; Leo clock; Read and Write
This is the set of hardware opcodes used to control the manipulation of data in the Format Converter. The main function of the opcodes is to direct the order that the data is read out of the Bucket Buffer and the conversion that is applied to the data.
The hardware uses the opcodes in the following order: VCS OP[0] ...VCS OP[12]. Each of the VCS OP opcodes consists of a Packet Opcode and a Packet Relative Address. The Packet Opcode controls the format conversion as shown in Table 5-6. The Packet Relative Address is the address of the input data word relative to the packet base address in the Bucket Buffer.
The Header opcode is treated differently and causes different actions depending on its location in the VCS Opcode memory. If the Header opcode is placed in the first location of VCS Opcode memory, the header value from the Bucket Buffer is sent unmodified to the Output Control logic to be used as the vertex header. If the first location of VCS Opcode memory does not contain a header opcode, the contents of the "Auxiliary Vertex Header" register (see page 5-66) are inserted into the data stream becoming, in effect, the vertex header. This is for cases where a constant header is required and the vertex headers in the input data are ignored or for input data not containing a header.
There is one more condition. If the Header opcode is placed in locations other than the first in the VCS Opcode memory, the contents of the "XGL Constant" register (see page 5-67) are inserted into the data stream. This is for cases where insertion of an extra constant into the data stream is required; like insertion of a Z value into a 2-D input data stream to make it a 3-D data stream.
Table 5-6 Data Format Conversion for VCS Opcodes
------------------------------------------------------------------------------------
VCS OP<7'> VCS OP<6'> VCS OP<5'> Opcode Description ------------------------------------------------------------------------------------
0 0 0 Data<15:8 Y Float<31:0 (Red)
0 0 1 Data<23:16 Y Float<31:0 (Green)
0 1 0 Data<31:24 Y Float<31:0 (Blue)
0 1 1 Header Y (See Usage text for details)
1 0 0 Double Float<63:0 Y Float<31:0'>
1 0 1 Data<31:0 Y Data<31:0'>
1 1 0 Data<15:0 Y Float<31:0 (Nx, Nz)
1 1 1 Data<31:16 Y Float<31:0 (Ny)
------------------------------------------------------------------------------------
These State Set 1, Leo Clock Domain registers control the Vertex Buffer Memory. This memory area contains a Vertex Buffer, a three-word Alternate Vertex Tupple 1 buffer, a three-word Alternate Vertex Tupple 2 buffer, a three- word Alternate Vertex Tupple 3 buffer, a LeoFloat Dispatch register, a Pass Through Header register, a Subelement Pick ID register, and a Pass Through Mode Control register.
0x120 1000 thru 0x120 10BF (48 words = 192 bytes)
State Set 1 only; Leo clock; Read and Write
The Vertex Buffer shown above contains an example of the data that may be present along with identifying tupples that are used in the text. Note that the Vertex Buffer is partitioned into four segments of 12 32-bit words. Each 12-word group is associated with the x, y, z, normal, and color for one vertex. The buffer can therefore hold up to four vertices at one time.
In normal operation, the Vertex Buffer is automatically written by the hardware from the Bucket Buffer under control of the VCS Opcodes. It accumulates vertices that are read out of the Bucket Buffer and processed through the Format Converter. When enough vertices are gathered for a primitive, the vertices are put together into a primitive packet and sent from the LeoCommand chip to the LeoFloat chip across the CFBus.
Software does not normally write into the Vertex Buffer. However, it can write patterns into this buffer and read them out for diagnostic purposes.
Certain constant registers are also stored in the Vertex Buffer memory area - see Alternate Vertex Tupple 1, Tupple 2, and Tupple 3, which are described next. Note that the software writes into the Alternate Vertex Tupple registers to set them up.
0x120 10C0 thru 0x120 10C8 (3 words = 12 bytes)
State Set 1 only; Leo clock; Read and Write
The output logic may substitute the alternate tupple 1 for the first tupple controlled by bits in the "LC Output Format" register (see page 5-61). Note that this is words 48, 49, and 50 of the Vertex Buffer memory.
0x120 10CC thru 0x120 10D4 (3 words = 12 bytes)
State Set 1 only; Leo clock; Read and Write
The output logic may substitute the alternate tupple 2 for the second tupple controlled by bits in the "LC Output Format" register (see page 5-61). Note that this is words 51, 52, and 53 of the Vertex Buffer memory.
0x120 10D8 thru 0x120 10E0 (3 words = 12 bytes)
State Set 1 only; Leo clock; Read and Write
The output logic may substitute the alternate tupple 3 for the third tupple controlled by bits in the "LC Output Format" register (see page 5-61). This is a special tupple that is included only on a per primitive basis. It is sometimes called the XGL facet normal tupple. Note that this is words 54, 55, and 56 of the Vertex Buffer memory.
0x120 10E4
State Set 1 only; Leo clock; Read and Write
The contents of this register are attached to the beginning of all primitives. It is the first location transmitted on the CFBus for each primitive packet sent to the LeoFloat chips. It is followed by the contents of the Vertex Buffer.
The software does not compile the dispatch opcode into the vertex list. The value sent to the LeoFloat chip consists of the Vertex Header (from the current vertex) and the Dispatch Opcode field. The total 15-bit value becomes the first half word of the LeoFloat primitive. The Dispatch Opcode field becomes the dispatch address to the microcode in the LeoFloat chip. The LeoDispatch is only used for "vertex" primitives and not for pass through packets. Note that this is word 57 of the Vertex Buffer.
Note - The Host software only needs to be concerned with the loading Dispatch Opcode field of this register. The Vertex Header part, even though it is readable and writable, is modified by hardware during processing of vertex primitives and changes during that time. Any values that may have been written into it by software are not used and are not guaranteed to be there after processing of vertex data. The Vertex Header field does not have to be saved and restored for context switches (but doing so is not a problem). The Dispatch Opcode does have to be saved and restored for context switches.
The example below shows the first part of the packet sent to the LeoFloat chip.
D<14:9 = Vertex Header
The Vertex Header contains two types of bits: (1) Highlight Edge bits, which
are rendered with edge color if the corresponding bit is on (and the edge mode
is active), and (2) Hollow Edge bits, which are rendered in Hollow triangles
(with lighted colors) if the corresponding bit is on. This field is coded as
follows:
D<14 = Hollow edge between vertices 1 and 2
D<13 = Hollow edge between vertices 3 and 1
D<12 = Hollow edge between vertices 2 and 3
D<11 = Draw highlighted edge between vertices 1 and 2
D<10 = Draw highlighted edge between vertices 3 and 1
D<9 = Draw highlighted edge between vertices 2 and 3
Note that 1 is the oldest, 2 is the middle, and 3 is the newest vertex.
D<8:0 = Dispatch Opcode
This field becomes the dispatch address to the microcode in the LeoFloat chip.
Table 5-7 shows the currently assigned dispatch opcodes.
Table 5-7 LeoFloat Dispatch Opcode
--------------------------------------------------------------------------------------------------------
Opcode Function Opcode Function --------------------------------------------------------------------------------------------------------
000 Cold initialization 040 Picking Enabled
001 Plain Dot 041 Face Culling Method
002 RGB Dot 042 Use Back Props
003 Dot with Normals 043 Front Lighting Degree
004 Dot with RGB and Normals 044 Inverse View Matrix
005 Plain Vector 045 Facet Normal Enable
006 RGB Vector 046 Front Surface Color
007 Vector with Normals 047 Back Surface Color
008 Vector with RGB and Normals 048 Eye Vector Properties
009 Triangle with Normals 049 Front Material Properties Cached
010 Triangle with RGB 050 Back Material Properties Cached
011 Triangle with RGB and Normals 051 Light Sources Cached
012 Hollow Triangle with Normals 052 Front Material Properties Uncached
013 Hollow Triangle with RGB 053 Back Material Properties Uncached
014 Hollow Triangle with RGB and Normals 054 Light Sources Uncached
015 Raster Data Copy 055 Light Counters
016-031 Reserved for other geometry functions (nurbs, 056 Front Specular Color
etc.)
032 Pass Through 057 Back Specular Color
033 Load Context 058 Raster XY Position
034 Store Context 059 Model Clipping Enabled
035 Matrix Processing (NPC) 060 Model Clip Planes Load Matrix
036 View Matrix Processing (NPC) 061 Diagnostic Mode (Sundiag SRAM Selftest)
037 Poke Matrix 062 Read Micro Rev Level
038 Matrix Processing (LC) 063 Build Dot Branch Tables
039 Not Used 064 Build Vector Branch Tables
065 Build Triangle Branch Table 068-080 Reserved
066 Back Light Degree 081-128 Undefined
067 Model Clipping Number
--------------------------------------------------------------------------------------------------------
0x120 1428
State Set 1 only; Leo clock; Read and Write
The Pass Through Header can be attached to the beginning of the packet sent to the LeoFloat chip for pass through packets. See the Pass Through Header Enable field of the "Pass Through Mode Control" register on page 5-59.
0x120 1434
State Set 1 only; Leo clock; Read and Write
This register contains either the Subelement Pick ID or a Pass Through Packet count value.
For the Subelement Pick ID, the LeoCommand chip can create this alternate pick code and send it as a part of the primitive packets sent to the LeoFloat chip. To initialize the value, the software writes to this register. The output logic inserts this value into the output packet and increments its value as controlled by bits in the vertex header and the "Vertex Mode Control" register (see page 5-42). The dispatch opcode remains the first half word, but this pick code becomes the second half word:
For the Pass Through Packet count value, the hardware loads a count value into this register that identifies the packet being sent to the LeoFloat chips. See the Pass Through Header Counter Enable bit of the "Pass Through Mode Control" register on page 5-59 for details.
This register is not cleared on reset. The software must load the desired value into this register before using it.
0x120 1424
State Set 1 only; Leo clock; Read and Write
The fields of this register affect how the LeoCommand chip prepares Pass Through Packets for the LeoFloat chips.
D<10 = Pass Through DMA Mode
Specifies the mode used for the Pass Through packets:
D<9:8 = Pass Through Header Counter Enable
Specifies whether to prepend the contents of the Pass Through Header register
to the packet and the contents of the Subelement Pick ID register to the packet.
The typical use for the counter is when using Pass Through packets for Raster
Copy and a count value is required to identify the packet being sent to the
LeoFloat chips. The value of the counter is incremented for each packet sent to
the LeoFloat chips when it is enabled to be sent. This field is coded as follows:
D<7 = Pipeline Order
Specifies if the hardware scoreboard logic is to maintain the packet
order - send outputs from the LeoFloat chips to the LeoDraw chips in the same
order as packets went from the LeoCommand chip to the LeoFloat chips.
D<6 = Packet Output
Specifies if this LeoFloat packet may create one or more LeoDraw packets from
the LeoFloats:
D<5:4 = Unicast Select
Specifies which LeoFloat chip receives a packet that is sent:
D<3:2 = Packet Destination
<-HangingPara_noSA > 00 Unicast (send to next available LeoFloat) <-HangingPara_noSA > 01 Unicast (send to a specific LeoFloat) <-HangingPara_noSA > 10 Unicast (send to the same LeoFloat that the last packet was sent to) <-HangingPara_noSA > 11 Multicast (broadcast to all LeoFloats). Note that multicast packets are used to send attributes to LeoFloats. They never produces output packets from LeoFloats.D<1:0 = Packet Type
<-HangingPara_noSA > 0x Normal Pass Through <-HangingPara_noSA > 10 Read the firmware memory (LeoFloat SRAM) <-HangingPara_noSA > 11 Write the firmware memory (LeoFloat SRAM)These State Set 1, Leo Clock Domain registers control the Vertex Output Logic. There are two registers: the LeoFloat Output Format register and the Vertex Buffer State Machine register.
0x120 143C
State Set 1 only; Leo clock; Read and Write
The fields of this register affect the LeoFloat chip output format.
D<9:7 = Tupple Substitute Enable
Specifies whether to replace the source tupple with the Alternate Vertex
Tupple. For example, this is used when doing a pick echo or when
highlighting, where the per vertex color is substituted with a constant
highlight color from the Alternate Vertex Tupple. This field is coded as follows:
D<6:5 = Tupple Replicate Enable
Specifies whether to replicate the appropriate tupple for the vertex data sent to
the LeoFloat chip. One use of this feature is to take facet data (which is in the
vertex that is the header source) and replicate it to the other vertices to turn the
data into vertex data. The microcode in Leo still processes it as data per vertex.
This field is coded as follows:
D<4:2 = Vertex Float To Fixed Compression
Specifies whether to compress the tupples. In this case, the output logic
converts the 32-bit float values of the Vertex Buffer into 16-bit fixed values
before it places the values on the Leo CFBus. Normally the software should
always compress the tupples. This field is coded as follows:
D<1:0 = Vertex Format
Specifies the tupple count. This field must match the Vertex Format field of the
"Vertex Mode Control" register (see page 5-42). Both the format logic and the
output logic cache this value. This field is coded as follows:
0x120 1458
State Set 1 only; Leo clock; Read and Write
The Vertex Buffer state machine is the logic that transfers words from the vertex buffer to the CFBus. For context switches, the state of this machine and associated parameters must be saved and restored to ensure proper operation. This register holds that state. The complete context of one restored environment consists of the contents of this register, the Bucket Buffer State Machine register, all other accelerator port registers, and the locations of the buffers. Other than saving and restoring the context, software normally does not read or write this register.
The five 4-bit fields specified in bits 19 through 0 contain pointers to the various temporal vertex identities. These pointers refer to the base address of one of the four vertex segments, each of which are 12 words long. The base pointer fields are codes as follows:
00 points to the Vertex Buffer (first segment)
01 points to hex location c in the Vertex Buffer (second segment)
10 points to hex location 18 in the Vertex Buffer (third segment)
11 points to hex location 24 in the Vertex Buffer (fourth segment)
When the vertex mode is off or after reset, the initial condition of D<19:0 is set to 0011 0011 0001 0010 0000. Thus, the Control Pointer and the Oldest Pointer point to the fourth segment, the Mid Pointer points to the second segment, and the Newest Pointer points to the third segment, and the Buffer Pointer points to the first segment.
When vertex mode is on with just the first three vertices of a series stored in the Vertex Buffer, D<19:0 is equal to 1011 1011 1001 1010 0000. Note that the first bit in a pointer field is set to "1" if the segment contains valid data.
With normal replacement after the first triangle primitive is sent to a float, but before the next vertex is loaded, D<19:0 equals 1001 1001 1010 0000 0011. Thus, the Oldest Pointer now points to the second segment (this was the middle vertex), the Mid Pointer points to the third segment (this was the newest vertex), and the Newest Pointer points to the first segment (this was the buffer available for the next vertex). Note that the first bit of the Newest Pointer is "0" because this segment does not yet contain valid data.
D<30:27'> = Flags
Specifies the interim state of the Vertex Buffer controllers for the vertex buffer
pointer and primitive output sequence control for partial primitives. This field
contains encoded context status flags of type:
Back Face Header
Multiple Edge IDs
Disjoint Odd
Second Triangle
Context idle states are limited to those that can occur prior to the completion of cf_bus output for the first vertex set. (A three vertex set can generate up to three edge primitives.)
D<26:24 = Gen Control
Specifies the context state of the Command Generator State Machine. The
context states are:
D<23:20 = Vertex Control
Specifies the state of the Vertex Control State Machine, which controls the
loading of and access to the Vertex Buffer. The context states are:
D<19:16= Control Pointer
Specifies the current control header base pointer for the oldest mode (XGL).
D<15:12 = Oldest Pointer
Specifies the first occurring vertex of a triangle primitive when normal
replacement occurs.
D<11:8 = Mid Pointer
Specifies the second occurring vertex.
D<7:4 = Newest Pointer
Specifies the third occurring vertex.
D<3:0 = Buffer Pointer
Specifies the location where the fourth vertex is loaded.
These State Set 1, Leo Clock Domain registers control the Miscellaneous LeoCommand operations.
0x120 142C
State Set 1 only; Leo clock; Read and Write
The contents of this register are used as a header when the first location of the VCS Opcode memory does not contain a "Header" opcode. See "VCS Opcode" on page 5-49 for a description of the opcodes.
D<7 = Increment CEN
Increment the Current Element Number. This is the value in the Pick ID
register.
D<6:5 = Hollow Edge Control
Coded as follows:
D<4 = Counter Clockwise
<-HangingPara_noSA > 0 Define triangle as clockwise (Vold, Vmid, Vnew) <-HangingPara_noSA > 1 Define triangle as counter-clockwise (Vold, Vnew, Vmid)
D<3:2 = General Triangle List Control
Coded as follows:
D<1 = Draw Other Edge
For triangles, draw an edge from the newest vertex to the oldest vertex.
Ignored for lines.
D<0 = Draw Edge
For triangles, draw an edge from the newest vertex to the second oldest vertex.
For lines, draw a line from the newest vertex to the previous vertex. A "0" is
equivalent to a "move" and a "1" to a "draw."
0x120 1430
State Set 1 only; Leo clock; Read and Write
The contents of this register are inserted in the data stream to the Vertex Buffers when a "Header" opcode is encountered in any location of the VCS Opcode memory except the first location. See "VCS Opcode" on page 5-49 for details.
0x120 145C
State Set 1 only; Leo clock; Read and Write
This register contains some bits from the vertex header along with some other data to supplement output from the Vertex Buffer. The contents of this register must be saved and restored for context switches. Other than context switching, the software should not access this register.
Initialized to the proper state by a reset.
0x120 1460
State Set 1 only; Leo clock; Read and Write
This register contains some bits from the vertex header along with some other data to supplement output from the Vertex Buffer. The contents of this register must be saved and restored for context switches. Other than context switching, the software should not access this register.
Initialized to the proper state by a reset.
0x120 1464
State Set 1 only; Leo clock; Read and Write
This register contains some bits from the vertex header along with some other data to supplement output from the Vertex Buffer. The contents of this register must be saved and restored for context switches. Other than context switching, the software should not access this register.
Initialized to the proper state by a reset.
0x120 1468
State Set 1 only; Leo clock; Read and Write
This register contains some bits from the vertex header along with some other data to supplement output from the Vertex Buffer. The contents of this register must be saved and restored for context switches. Other than context switching, the software should not access this register.
Initialized to the proper state by a reset.
0x120 0000
State Set 1 only; Leo clock; Write only
Specifies which LeoFloat chips are enabled to receive LeoFloat packets. This enable takes precedence over the Unicast Select field of the "Pass Through Mode Control" register (see page 5-59).
D<4 = BLT Mode
BLock Transfer (BLT) Mode is used by Leo 48 for Block Copy/Fill.
D<3:0 = LeoFloat Enable Mask
Specifies the LeoFloat chips that receive LeoFloat packets. This field is coded as
follows:
0x120 0004
State Set 1 only; Leo clock; Write only (Strobe)
Writing to this location sends an Interrupt/Run condition to the LeoFloat chips over the CFBus. The LeoFloat Enable Mask field of the "LeoFloat Enable Mask" register (see page 5-70) determines which LeoFloat chip actually receives the Interrupt/Run condition. This is a "strobe" location - the data is a "don't care."
0x120 0828
State Set 1 only; SBus clock; Write only (Strobe)
Writing to this location resets the Accelerator Port in the LeoCommand chip. The reset condition stays active and needs to be inactivated by the "Clear Accelerator Port Reset" strobe. This is a "strobe" location - the data is a "don't care."
0x120 082C
State Set 1 only; SBus clock; Write only (Strobe)
Writing to this location deactivates the reset condition for the Accelerator Port in the LeoCommand chip. If the reset condition is not active, nothing happens. This is a "strobe" location - the data is a "don't care."
0x020 0008
State Set 0 only; Leo clock; Write only (Strobe)
Writing to this location clears the LeoDraw Semaphore status bit in the "Leo System Status" register. This is a "strobe" location - the data is a "don't care."
0x120 1404
State Set 1 only; Leo clock; Write only (Strobe)
Writing to this location activates the Accelerator Port in the LeoCommand chip for accepting vertex packets (dots, vectors, triangles). This should be set last to start processing after all other controls in the other registers are set, but before the DMA (if DMA is used) is started. This is a "strobe" location - the data is a "don't care."
Note that the system must be in one of four modes: Vertex Mode, Pass Through Mode, Context Switch Mode, or Idle Mode.
0x120 1408
State Set 1 only; Leo clock; Write only (Strobe)
Writing to this location activates the Accelerator Port in the LeoCommand chip for accepting Pass Through packets. This should be set last to start processing after all other controls in the other registers are set, but before the DMA (if DMA is used) is started. Raster Copy mode also needs to set Pass Through mode. This is a "strobe" location - the data is a "don't care."
Note that the system must be in one of four modes: Vertex Mode, Pass Through Mode, Context Switch Mode, or Idle Mode.
0x120 140C
State Set 1 only; Leo clock; Write only (Strobe)
Writing to this location prepares the Accelerator Port in the LeoCommand chip for context switching - the port does an orderly completion of its current processing and then goes into Idle Mode. The Bucket Buffer Busy and Vertex Buffer Busy fields of the Accelerator Port Status register indicate when the idle state is reached and therefore when context switching can occur. At that time, the current context should be saved, new context restored, and the Context Mode exited by accessing the "Exit Vertex, Pass Through, or Context Mode" location (see page 5-75). This is a "strobe" location - the data is a "don't care."
Note that the system must be in one of four modes: Vertex Mode, Pass Through Mode, Context Switch Mode, or Idle Mode.
It is important to note that the Accelerator Port is always completely drained after the port enters the Context Switch mode. The maximum content when the port controllers reach their final context state is:
DMA Read off.
A partial/null packet in Bucket Buffer
None, one, or two vertices in Vertex Buffer.
Scoreboard empty (after a long Float drain delay ).
Dynamic control context is solely contained in the "Bucket Buffer State Machine" register, the "Vertex Buffer State Machine" register, and the header registers. Data is in the two buffers. Static context is restored in the Accelerator Port file of control registers.
0x120 1410
State Set 1 only; Leo clock; Write only (Strobe)
Writing to this location completes and exits the Vertex, Pass Through, or Context Mode for the Accelerator Port in the LeoCommand chip. The exit from Vertex Mode flushes any leftover data from the Vertex Buffers (used as a reset between vertex strips) and places the system in Idle Mode. In general, this exit resets the current state in the Accelerator Port. This is a "strobe" location - the data is a "don't care."
0x120 1400
State Set 1 only; Leo clock; Read only
This register contains the Accelerator Port status. Note that bits 4 through 6 indicate when it is safe to write a register - they define the region of safety for software synchronization. This is a read only location.
D<11> = Vertex Buffer Busy Status
The Vertex Buffer Busy Status can not go idle before the Bucket Buffer Busy
Status goes idle. Therefore, when Vertex Buffer Busy Status = 0, both the
Bucket Buffer and the Vertex Buffer are idle.
D<10> = Bucket Buffer Busy Status
<-HangingPara_noSA > 0 Bucket Buffer control is idle <-HangingPara_noSA > 1 Bucket Buffer control is busy
D<9> = Bucket Buffer Space Available Status
This bit must be checked before the software starts writing any packet in
immediate mode.
D<8> = Context Mode Status
<-HangingPara_noSA > 0 Context switch mode not active <-HangingPara_noSA > 1 Context switch mode activeD<7> = Pass Through Mode Status
<-HangingPara_noSA > 0 Pass Through mode not active <-HangingPara_noSA > 1 Pass Through mode activeD<6> = Vertex Mode Status
<-HangingPara_noSA > 0 Vertex mode not active <-HangingPara_noSA > 1 Vertex mode activeD<5> = DMA Mode Status
<-HangingPara_noSA > 0 Immediate mode active <-HangingPara_noSA > 1 DMA mode active
D<4:0 = Bucket Buffer Words Available
Indicates the number of words available in the Bucket Buffer for new data.
0x120 146C
State Set 1 only; Leo clock; Read and Write
Allows software to save and restore (for context switching) the identification code of the last LeoFloat chip that was loaded.
D<1:0 = Last Float Loaded
Specifies the last LeoFloat chip that was loaded:
