8 RAMDAC Registers



8.1 Address Map

The RAMDAC address space is complex in that it is shared by the RAMDAC and LeoCross. Furthermore, access to the RAMDAC and LeoCross internal state is of two types, direct and indirect.

The indirect type of access requires two SBus transactions. In the first transaction, the software writes an index value into the RAMDAC Address Pointer register, which points to the register or memory that is to be accessed in a following transaction. In the second transaction, the actual register or memory identified in the address map by that index is accessed. The RAMDAC automatically increments the address pointer to accommodate access to contiguous memory locations in the Color Table.

The RAMDAC Address Map is shown in Table 8-1 for State Set 0. Note that the mapping occurs twice, once for State Set 0 and once for State Set 1. To access State Set 1, add 0x100 000 to the SBus address shown for State Set 0. In this table, the locations are listed in order by SBus address and then by index value. However, the registers are described in this chapter in a functional order. The page column in the Address Map refers to the page where that register is described.

    Table 8-1 RAMDAC Address Map - State Set 0 

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Page   SBus         Index   Access  Register
       Address                                                
----------------------------------------------------------


                                    
8-2    0x060 0020   Direct  R/W     RAMDAC Address Pointer
                                    
8-7    0x060 0024   0x00    R/W     Color Table, Word 0
                     Ø                Ø
                    0xFF            Color Table, Word 255
                                    
8-10   0x060 0028   0x00    Read    Pixel Test
                                    
8-10   0x060 0028   0x01    R/W     DAC Test
                                    
8-11   0x060 0028   0x02    R/W     Sync, Blank, & IPLL Test
                                    
8-9    0x060 0028   0x03    Read    ID
                                    
8-9    0x060 0028   0x04    R/W     Pixel Mask
                                    
8-5    0x060 0028   0x06    R/W     Command Register 2
                                    
8-6    0x060 0028   0x07    R/W     Command Register 3
                                    
8-3    0x060 002C   Direct  R/W     RAMDAC Mode

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8.2 Register Data Formats

This section describes the data formats of the registers in the RAMDAC Register Address Space.

8.2.1 RAMDAC Address Pointer

Address

0x060 0020 for State Set 0
0x160 0020 for State Set 1

Conditions

State Set 0 and 1; Read and Write

Usage

This is the RAMDAC address pointer used to point to the indirectly accessed memory and registers.

8.2.2 RAMDAC Mode

Address

0x060 002C for State Set 0
0x160 002C for State Set 1

Conditions

State Set 0 and 1; Read and Write

Usage

The RAMDAC Mode register controls various RAMDAC operations as described in the "Bit Fields" section.

Bit Fields

D<7:6 = Palette Select Control
Allows up to four palette devices (color tables) to work together. Each palette device contains 256 30-bit words. Only one palette device may be selected at any particular instant. The control signals for these bits are multiplexed, allowing for sub-pixel resolution. This allows up to four windows to be controlled by separate palettes. For Leo, these bits are normally set to 00.

<-HangingPara_noSA > 00 Selects Palette 0 <-HangingPara_noSA > 01 Selects Palette 1 <-HangingPara_noSA > 10 Selects Palette 2 <-HangingPara_noSA > 11 Selects Palette 3

D<4:3 = Operational Mode Control
These bits allow debugging of the RAMDAC and its interface to other devices. Test registers monitor the pixel port, RAM, and the DAC port. The RAMDAC Mode register and Control Register 2 control the test modes. Data is latched in the test registers along the video path by either the pixel clock or by using bit 7 of the Red pixel data as a trigger bit. The pixel data trigger is useful when the pixel clock is connected to a free running source.

<-HangingPara_noSA > 00 Normal mode. In this mode, both the Pixel Test and DAC Test registers are triggered every clock cycle. This is useful when there is independent control over the clock. By stopping the clock in the low state, the data in the test registers can be read out and verified. <-HangingPara_noSA > 01 Fast Trigger (Pixel Data Path) Test (R7). In this mode, each test register trigger is activated by a transition of red bit 7 (R7) of the pixel port. Bit 0 of Command Register 2 controls whether the trigger is activated by a rising edge or a falling edge of R7. Once the data is captured, it can be read out at any time, even if the pattern is cyclical with the same pixel repeatedly activating the trigger. <-HangingPara_noSA > 10 RAM/Fast Port Test. In this mode, the DAC Test register is triggered every clock cycle. Data written into the Pixel Test register enters the fast data-path, passes through the palette, and gets captured at the DAC Test register. <-HangingPara_noSA > 11 DAC Test. In this mode, data is written into the DAC Test register and the Sync, Blank, & IPLL Test register is reflected at the DAC outputs. This allows the DACs to be tested over the micro port.

D<2 = CXBus Data Width
Specifies the data bus width of the CXBus.

<-HangingPara_noSA > 0 Sets the data bus width to 8 bits. In this mode, 10 bits of data may be written to the RAMDAC. The eight most-significant bits are written first on bits 7 through 0, then the two least-significant bits of the 10-bit DACs are written on bits 1 and 0. Data bus bits 9 and 8 are zeroes in 8-bit mode. <-HangingPara_noSA > 1 Sets the data bus width to 10 bits.

D<1 = Resolution Control
Specifies the resolution control.

<-HangingPara_noSA > 0 Sets the RAM depth to 24 bits (8 bits each for red, green, and blue) and each of the three DACs for a resolution of 8 bits. The least significant bits of the 10-bit DACs are pulled down to zero. <-HangingPara_noSA > 1 Sets the RAM depth to 30 bits (10 bits each for red, green, and blue) and each of the three DACs for a resolution of 10 bits.

D<0 = Reset Control
Resets the pixel port sampling sequence to ensure that the pixel sequence AB starts at A. To reset the sampling sequence, write a 1, then a 0, and then a 1 to this bit.

8.2.3 Command Register 2

Address

0x060 0028, index 0x06, State Set 0
0x160 0028, index 0x06, State Set 1

Conditions

State Set 0 and 1; Read and Write

Usage

This is a 10-bit register that contains the control bits described under "Bit Fields" below. Only 8 bits are used.

Bit Fields

D<7:4 = True Color & Pseudo Color Mode Control
Specify the color mode. The three 8-bit Pseudo Color modes allow the pixel input data to be encoded on the red, green, or blue input pixel stream.

<-HangingPara_noSA > 00xx 8-bit Pseudo Color on R7:R0 <-HangingPara_noSA > 01xx 8-bit Pseudo Color on G7:G0 <-HangingPara_noSA > 10xx 8-bit Pseudo Color on B7:B0 <-HangingPara_noSA > 1100 12-bit True Color on R7:R4, G7:G4, B7:B4 <-HangingPara_noSA > 1101 12-bit True Color on R6:R3, R1:R0, G6:G5, G3:G0 <-HangingPara_noSA > 111x 24-bit True Color on R7:R0, G7:G0, B7:B0

D<3 = Pedestal Enable Control
Specifies whether a 0 IRE or a 7.5 IRE blanking pedestal is generated on the video outputs.

<-HangingPara_noSA > 0 0 IRE <-HangingPara_noSA > 1 7.5 IRE

D<2 = Sync Recognition Control
Specifies whether the video sync input is encoded onto the analog video current outputs or ignored.

<-HangingPara_noSA > 0 Ignore <-HangingPara_noSA > 1 Decode

D<1 = IPLL Trigger Control
Specifies whether the IPLL output is triggered from blank or sync.

<-HangingPara_noSA > 0 Sync <-HangingPara_noSA > 1 Blank

D<0 = R7 Trigger Polarity Control
Determines whether the pixel data is latched into the test registers on the rising or falling edge of red bit 7 (R7).

<-HangingPara_noSA > 0 Rising edge <-HangingPara_noSA > 1 Falling edge

8.2.4 Command Register 3

Address

0x060 0028, index 0x07, State Set 0
0x160 0028, index 0x07, State Set 1

Conditions

State Set 0 and 1; Read and Write

Usage

This is a 10-bit register that contains the control bits described under "Bit Fields" below. Only 8 bits are used.

Bit Fields

D<7:6 = Pixel Multiplexer Control
Specify the RAMDACs multiplex mode. It thus also determines the frequency of the loadout signal. Loadout is a divided down version of the pixel clock.

<-HangingPara_noSA > 00 1:1 Muxing - Loadout = Clock/1 <-HangingPara_noSA > 01 2:1 Muxing - Loadout = Clock/2 <-HangingPara_noSA > 10 Reserved <-HangingPara_noSA > 11 Reserved

D<5:2 = Extra Blank Pipeline Delay Control
Specify the additional pipeline delay that can be added to the blank function, relative to the overall RAMDAC pipeline delay. As the blank control normally enters the Video DAC from a shorter pipeline than the video pixel data, this control is useful in de-skewing the pipeline differential.

<-HangingPara_noSA > 0000 Overall pipeline delay <-HangingPara_noSA > 0001 Overall pipeline delay + 1 \xb4 Loadout <-HangingPara_noSA > 0010 Overall pipeline delay + 2 \xb4 Loadout <-HangingPara_noSA > . . . <-HangingPara_noSA > 1111 Overall pipeline delay + 15 \xb4 Loadout

D<1:0 = Prgckout Frequency Control
Specify the output frequency of the Prgckout output from the RAMDAC. Prgckout is a divided down version of the pixel clock.

<-HangingPara_noSA > 00 Clock/4 <-HangingPara_noSA > 01 Clock/8 <-HangingPara_noSA > 10 Clock/16 <-HangingPara_noSA > 11 Clock/32

8.2.5 Color Table

Address

0x060 0028, index = 0x00 thru 0xFF (256 words), State Set 0
0x160 0028, index = 0x00 thru 0xFF (256 words), State Set 1

Conditions

State Set 0 and 1; Read and Write

Usage

The RAMDAC Color Table contains 256 30-bit words. It is normally thought of as three 256 word by 10-bit color lookup tables for the red, green and blue outputs.

The color palette may be programmed to be 24-bits deep (eight bits for red, green, and blue) instead of 30 (ten bits each). When configured as 24 bits deep, the least-significant bits of the ten-bit digital-to-analog converters are pulled down to zero, allowing for 256 output levels instead of 1024.

Access to the color table requires several operations. The first operation is a write to load the "RAMDAC Address Pointer" register with address of the starting word in the color table. The remaining operations depend whether the resolution control (see "RAMDAC Mode" register on page 8-3) is set for 8-bit or 10-bit mode.

When writing to or reading from the color table on a sequential basis, only the starting address needs to be specified. After a red, green, and blue access sequence, the address increments automatically.

For 8-bit mode, the second through fourth accesses of the color table are for the red, green, and blue tables, respectively. After the fourth access, the address increments automatically.

For 10-bit mode, six accesses of the color table are required before the address increments automatically. These accesses proceed in the following order:

    Access the eight most-significant bits of the red color table.

    Access the two least-significant bits of the red color table. These two bit values correspond to data bits 1 and 0 of the SBus.

    Access the eight most-significant bits of the green color table.

    Access the two least-significant bits of the green color table. These two bit values correspond to data bits 1 and 0 of the SBus.

    Access the eight most-significant bits of the blue color table.

    Access the two least-significant bits of the blue color table. These two bit values correspond to data bits 1 and 0 of the SBus.

The RAMDAC Color Table is used to provide gamma correction. Gamma correction solves two problems. First, it converts the linear coded color values stored in the LeoCross CLUTs to ratio values for display on the monitor. The ratio values are used because the eye is sensitive to ratios of intensity levels rather than their absolute values. Second, gamma correction compensates for any non-linearity in the monitor.

8.2.6 Pixel Mask

Address

0x060 0028, index 0x04, State Set 0
0x160 0028, index 0x04, State Set 1

Conditions

State Set 0 and 1; Read and Write

Usage

The contents of this register are individually bit-wise logically ANDed with the red, green, and blue pixel input streams of data.

8.2.7 ID

Address

0x060 0028, index 0x03, State Set 0
0x160 0028, index 0x03, State Set 1

Conditions

State Set 0 and 1; Read only

Usage

Returns the value 0x8C, which identifies the RAMDAC as an Analog Devices ADV7152.

8.2.8 Pixel Test

Address

0x060 0028, index 0x00, State Set 0
0x160 0028, index 0x00, State Set 1

Conditions

State Set 0 and 1; Read only

Usage

Allows diagnostic access to the pixel port. The test modes are controlled by the "RAMDAC Mode" register and "Command Register 2." See D<4:3 of the "RAMDAC Mode" register on page 8-3 for details.

8.2.9 DAC Test

Address

0x060 0028, index 0x01, State Set 0
0x160 0028, index 0x01, State Set 1

Conditions

State Set 0 and 1; Read and Write

Usage

Allows diagnostic access to the DAC port. The test modes are controlled by the "RAMDAC Mode" register and "Command Register 2." See D<4:3 of the "RAMDAC Mode" register on page 8-3 for details.

8.2.10 Sync, Blank, & IPLL

Test

Address

0x060 0028, index 0x02, State Set 0
0x160 0028, index 0x02, State Set 1

Conditions

State Set 0 and 1; Read and Write

Usage

Allows diagnostic access to the three least significant bits of the sync, blank and IPLL pixel control bits. The test modes are controlled by the "RAMDAC Mode" register and "Command Register 2." See D<4:3 of the "RAMDAC Mode" register page 8-3 for details.

Note that IPLL is the phase locked loop output current that allows multiple RAMDACs to be synchronized with pixel resolution. This feature is not used for Leo.