The LeoDraw Chip registers are separated into Global and State Set dependent registers for the Direct Port (State Set 0) and Accelerator Port (State Set 1). For some functions, a separate register is provided in both State Set 0 and 1. The Global registers have one register that serves both State Sets - they can be accessed by both the Direct Port and the Accelerator Port.
The SBus address bits for the LeoDraw register address space are shown below.
A<24 = State Set
<-HangingPara_noSA > 0 Access State Set 0 (address 0x040 0XXX) <-HangingPara_noSA > 1 Access State Set 1 (address 0x140 0XXX). This bit is hardwired to 1 on the Accelerator Port.A<12 = Global
<-HangingPara_noSA > 0 Access State Set 0 or 1 registers (address 0x040 0XXX or 0x140 0XXX) <-HangingPara_noSA > 1 Access Global registers (address 0x040 1XXX or 0x140 1XXX)
A<11:9 = Specific Chip
Specifies the LeoDraw chip as follows:
There are five LeoDraw chips. The software may broadcast a write to all five chips or it can also narrowcast data to a specific LeoDraw chip. The Specific Chip field selects the desired chip mode as shown above. The broadcast is useful for setting some attribute that will be constant on all five chips.
Most LD registers contain the same information on all five chips. Thus, in most cases, it is only necessary to read the registers for chip 0. However, write and read the following registers for each chip (they contain unique information): LD Control and Status Register (CSR), LD Interleave, and Clear Pick Hit.
The LeoDraw Chip address maps for Global registers, State Set 0 registers, and State Set 1 registers are shown in Table 6-1 through Table 6-3. Note that the locations are listed in order by SBus address. However, the registers are described in this chapter in a functional order.
Table 6-1 LeoDraw Address Map - Global Registers
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
Page SBus Access Register Address ---------------------------------------------------------------------------------------------------------------------------------------------------------------------
6-33 0x040 1000 R/W Screen Start Address Left (Even)
6-33 0x040 1004 R/W Screen Start Address Right (Odd)
6-34 0x040 1008 R/W Screen Offset Left (Even)
6-35 0x040 100C R/W Screen Offset Right (Odd)
6-35 0x040 1010 R Video Counter
6-14 0x040 1020 R/W Frame Buffer Width
6-9 0x040 1024 R/W LD Interleave
6-13 0x040 1028 R LD Chip ID Code
6-11 0x040 102C W Set Stall LD Accelerator
6-12 0x040 1030 W Clear Stall LD Accelerator
6-12 0x040 1034 W Reset LD Accelerator Port
6-13 0x040 1038 W Clear LD Accelerator Port Reset
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
Table 6-2 LeoDraw Address Map - State Set 0 Registers
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Page SBus Access Register Address -----------------------------------------------------------------------------------------------------------------------------------------------------------
6-8 0x040 0000 R LD Control and Status Register (CSR)
6-39 0x040 0004 R/W Current Window ID
6-43 0x040 0008 R/W Window Write Mask
6-40 0x040 000C R/W WID Clip Mask
6-27 0x040 0010 R/W View Clip Minimum Bound
6-27 0x040 0014 R/W View Clip Maximum Bound
6-20 0x040 0020 R/W Stencil/Fill Foreground Color
6-22 0x040 0024 R/W Stencil Background Color
6-23 0x040 0028 R/W Copy/Scroll Source Address
6-25 0x040 002C R/W Copy/Scroll/Fill Destination Address
6-24 0x040 0030 R/W Copy/Scroll/Fill Size
6-38 0x040 0080 R/W Window Background Color
6-42 0x040 0084 R/W Image Write Mask
6-15 0x040 0088 R/W LD Attribute
6-41 0x040 008C R/W Constant Z Source
-----------------------------------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Page SBus Access Register Address -----------------------------------------------------------------------------------------------------------------------------------------------------------
6-8 0x140 0000 R LD Control and Status Register (CSR)
6-39 0x140 0004 R/W Current Window ID
6-43 0x140 0008 R/W Window Write Mask
6-40 0x140 000C R/W WID Clip Mask
6-27 0x140 0010 R/W View Clip Minimum Bound
6-27 0x140 0014 R/W View Clip Maximum Bound
6-30 0x140 0018 R/W Pick Minimum Bound
6-30 0x140 001C R/W Pick Maximum Bound
6-20 0x140 0020 R/W Stencil/Fill Foreground Color
6-22 0x140 0024 R/W Stencil Background Color
6-10 0x140 0040 W Set LD Semaphore
6-11 0x140 0044 W Clear LD Semaphore
6-28 0x140 0048 W Clear Pick Hit
6-37 0x140 004C R/W Fast Clear Data
6-44 0x140 0050 R/W Constant Alpha Source
6-38 0x140 0080 R/W Window Background Color
6-42 0x140 0084 R/W Image Write Mask
6-15 0x140 0088 R/W LD Attribute
6-41 0x140 008C R/W Constant Z Source
6-45 0x140 00A0 R/W Depth Cue Z-Front
6-46 0x140 00A4 R/W Depth Cue Z-Back
6-46 0x140 00A8 R/W Depth Cue Scale
6-47 0x140 00AC R/W Depth Cue Z-Scale
6-31 0x140 00B0 R/W Pick Front Bound
6-32 0x140 00B4 R/W Pick Back Bound
6-47 0x140 00B8 R/W Depth Cue Fade Color
6-44 0x140 00BC R/W Force Color
6-36 0x140 00C0 R/W Screen Door Column 1-0
6-36 0x140 00C4 R/W Screen Door Column 3-2
6-36 0x140 00C8 R/W Screen Door Column 5-4
6-36 0x140 00CC R/W Screen Door Column 7-6
6-36 0x140 00D0 R/W Screen Door Column 9-8
6-36 0x140 00D4 R/W Screen Door Column 11-10
6-36 0x140 00D8 R/W Screen Door Column 13-12
6-36 0x140 00DC R/W Screen Door Column 15-14
6-29 0x140 00E0 R/W Pick ID Register 0
6-29 0x140 00E4 R/W Pick ID Register 1
6-29 0x140 00E8 R/W Pick ID Register 2
6-29 0x140 00EC R/W Pick ID Register 3
6-29 0x140 00F0 R/W Pick ID Register 4
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Table 6-4 shows the registers that are common and unique to State Set 0 and State Set 1.
Table 6-4 State Set 0 and 1 Registers
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
SBus State Set 0 Register (0x040 XXXX) State Set 1 Register (0x140 XXXX) Address -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0xX40 0000 LD Control and Status Register (CSR) LD Control and Status Register (CSR)
0xX40 0004 Current Window ID Current Window ID
0xX40 0008 Window Write Mask Window Write Mask
0xX40 000C WID Clip Mask WID Clip Mask
0xX40 0010 View Clip Minimum Bound View Clip Minimum Bound
0xX40 0014 View Clip Maximum Bound View Clip Maximum Bound
0xX40 0018 Pick Minimum Bound
0xX40 001C Pick Maximum Bound
0xX40 0020 Stencil/Fill Foreground Color Stencil/Fill Foreground Color
0xX40 0024 Stencil Background Color Stencil Background Color
0xX40 0028 Copy/Scroll Source Address
0xX40 002C Copy/Scroll/Fill Destination Address
0xX40 0030 Copy/Scroll/Fill Size
0xX40 0040 Set LD Semaphore
0xX40 0044 Clear LD Semaphore
0xX40 0048 Clear Pick Hit
0xX40 004C Fast Clear Data
0xX40 0050 Constant Alpha Source
0xX40 0080 Window Background Color Window Background Color
0xX40 0084 Image Write Mask Image Write Mask
0xX40 0088 LD Attribute LD Attribute
0xX40 008C Constant Z Source Constant Z Source
0xX40 00A0 Depth Cue Z-Front
0xX40 00A4 Depth Cue Z-Back
0xX40 00A8 Depth Cue Scale
0xX40 00AC Depth Cue Z-Scale
0xX40 00B0 Pick Front Bound
0xX40 00B4 Pick Back Bound
0xX40 00B8 Depth Cue Fade Color
0xX40 00BC Force Color
0xX40 00C0 Screen Door Column 1-0
0xX40 00C4 Screen Door Column 3-2
0xX40 00C8 Screen Door Column 5-4
0xX40 00CC Screen Door Column 7-6
0xX40 00D0 Screen Door Column 9-8
0xX40 00D4 Screen Door Column 11-10
0xX40 00D8 Screen Door Column 13-12
0xX40 00DC Screen Door Column 15-14
0xX40 00E0 Pick ID Register 0
0xX40 00E4 Pick ID Register 1
0xX40 00E8 Pick ID Register 2
0xX40 00EC Pick ID Register 3
0xX40 00F0 Pick ID Register 4
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
This sections describes the data formats of the LeoDraw chip registers. The registers are described under the following functional groups:
"LD Control Registers" on page 6-8
"LD Attribute" on page 6-15
"Stencil Access" on page 6-20
"Block Copy" on page 6-23
"Viewport Clipping" on page 6-26
"Pick" on page 6-28
"Video Control" on page 6-32
"Screen Door Transparency" on page 6-36
"Fast Clear" on page 6-37
"Window IDs" on page 6-39
"Z-Plane Functions" on page 6-41
"Write Masks" on page 6-41
"Color/Alpha Registers" on page 6-43
"Depth Cueing" on page 6-45
There are eight LD Control Registers:
LD Control and Status Register (CSR)
LD Interleave
Set LD Semaphore
Clear LD Semaphore
Set Stall LD Accelerator
Clear Stall LD Accelerator
Reset LD Accelerator Port
Clear LD Accelerator Port Reset
LD Chip ID Code
Frame Buffer Width
0x040 0000 for State Set 0
0x140 0000 for State Set 1
Mapped into both State Set 0 and 1; Read only
This register is mapped into State Set 0 and 1, but can be read only over the direct port. Even though it is mapped into both state sets, there is only one LeoDraw CSR. It is a read only register.
D<7 = Acc Port Reset
Indicates that the LeoDraw accelerator port is in the reset state.
D<6:4 = Number of PID'S in LD Pipe
Indicates the number of pick ID's in the LeoDraw pipeline. This bit is used by
the LeoCommand chip to optimize the number of reads.
D<3 = LD Pick Hit
Indicates that the LeoDraw chip has found a pixel in the pick aperture. Reset
by the LeoCommand chip over the Direct Port.
D<2 = LD Semaphore
Indicates that the LeoDraw chip semaphore is set.
D<1 = Stall Acc
Indicates that a Stall Accelerator signal was received from the LeoCommand
chip.
D<0 = Acc Stalled
Indicates that an Accelerator Stalled signal is being sent to the LeoCommand
chip.
0x040 1024
Direct Port only: Global; Read and Write; not reset by a system reset
This register specifies the LD interleave value. It allows each LeoDraw chip to identify which of the five LD chips it is. This register must be initialized before the LD executes any Accelerated or Direct Port frame buffer access command.
D<2:0 = LD Interleave
Identifies the LeoDraw chip. Must be between 0 and 4.
0x140 0040
Accelerator Port only: State Set 1; Write (Strobe)
Note - Although this is a Global register, it is expected to be used only for the Accelerator Port and for State Set 1.
Writing to this location sets the LD Semaphore and therefore bit 2 of the LD CSR (see page 6-8). The LeoDraw chip does not execute any accelerator commands while this bit is set. This is a "strobe" location - the data is a "don't care." This address can be strobed over both the Accelerator and Direct Ports; it is expected that this address will never be used over the Direct Port.
0x140 0044
Direct Port only: State Set 1; Write (Strobe)
Writing to this location clears the LD Semaphore and therefore bit 2 of the LD CSR (see page 6-8). This allows the LeoDraw chip to resume frame buffer updates. This is a "strobe" location - the data is a "don't care." This address should be strobed over the Direct Port because the accelerator pipe stalls when the semaphore bit is set.
0x040 102C
LC only: Global; Write (Strobe)
Writing to this location sets bit 1 (ACC Stalled) of the LD CSR. The LeoDraw chip does not execute any accelerator commands while this bit is set. The LeoCommand chip uses this to lock out the accelerator during execution of Blt or Fill Direct Port operations. This register is for use by LeoCommand only. This is a "strobe" location - the data is a "don't care."
0x040 1030
LC only: Global; Write (Strobe)
Writing to this location clears bit 1 (ACC Stalled) of the LD CSR (see page 6-8) and allows the LeoDraw chip to resume frame buffer updates. This register is for use by LeoCommand only. This is a "strobe" location - the data is a "don't care."
0x040 1034
Global; Write (Strobe)
Writing to this location resets the LeoDraw accelerator port. It has the following effect on the LD CSR (see page 6-8):
Sets bit 7 - Acc Port Reset
Resets bit 3 - LD Pick Hit
Resets bit 2 - LD Semaphore
Resets bit 0 - Acc Stalled (To LC)
This is a "strobe" location - the data is a "don't care."
0x040 1038
Global; Write (Strobe)
Writing to this location clear the LeoDraw accelerator port reset condition. It also clears bit 7 (Acc Port Reset) of the LD CSR (see page 6-8). This is a "strobe" location - the data is a "don't care."
0x040 1028
Direct Port only: Global; Read only
This register contains a 32-bit id code that uniquely identifies the chip.
D<31:28 = Version
Specifies the version of the LeoDraw chip.
D<27:12 = Device Identification
The device identification code for the LeoDraw chip.
D<11:1 = JED Manufacturer Code
The JED manufacturer code assigned to Sun Microsystems or vender.
D<0 = 1
Always in the high state.
0x040 1020
Direct Port only; Read and Write
This register selects the frame buffer's maximum horizontal resolution. It also enables stereo addressing mode. This register is normally set only at configuration time.
0x040 0088 for State Set 0
0x140 0088 for State Set 1
Direct Port: State Set 0 and 1; Read and Write
Accelerator Port: State Set 0 and 1; Write only
This register contains several different control fields as explained under "Bit Fields".
For a Blend operation (bits 24 and 23) or Raster Operations (ROP) (bits 21 through 18), State Set 0 is used to specify the current ROP. The current ROP only affects the RGBO planes, depending on the current access mode plane group selected by the Plane Group enable field (bits 11 through 5). ROPs can not be performed on the Window ID, Z, or Fast Clear planes. Bit 4 (Force Current WID) must be zero (no blends). State Set 1 is used to specify the current boolean ROP or to enable the blend unit. The current ROP affects the RGBO, Cursor Data, and Cursor Enable planes only. The current blend operation affects the RGB planes only.
In the following bit field descriptions, SRC = source data, DST = data at frame buffer destination, BG = background, and DDA = Digital Differential Analyzer.
D<31:29 = Pick Control, State Set 1 only
Controls the LD picking unit. It is coded as follows:
Using these codes, the following functions can be used:
<-HangingPara > 0xx Disable picking <-HangingPara > 100 2-D Bound Pick without Render <-HangingPara_noSA > 101 3-D Bound Pick without Render <-HangingPara_noSA > 110 2-D Bound Pick while Render <-HangingPara_noSA > 111 3-D Bound Pick while RenderThe 2-D pick only uses X and Y bounds. The 3-D pick uses X, Y, and Z bounds.
D<28 = Depth Cue Enable, State Set 1 only
<-HangingPara_noSA > 0 Disable depth queuing <-HangingPara_noSA > 1 Enable depth queuing
D<27 = Screen Door Enable, State Set 1 only
Enables the screen door transparency feature:
D<26 = Force Color Enable, State Set 1 only
<-HangingPara_noSA > 0 SRC = DDA color <-HangingPara_noSA > 1 SRC = Color registerD<25 = Antialias Enable, State Set 1 only
<-HangingPara_noSA > 0 Constant alpha <-HangingPara_noSA > 1 Antialias filter alphaD<24 = Blend Function Select, State Set 1 only
<-HangingPara_noSA > 0 Blend to background: (SRC - BG) * alpha + DST <-HangingPara_noSA > 1 Blend to frame buffer: (SRC - DST) * alpha + DSTD<23 = Blend Enable, State Set 1 only
<-HangingPara_noSA > 0 Perform a raster operation as specified by ROP Code in bits 21-18. <-HangingPara_noSA > 1 Perform a blend operation as specified by Antialias Enable in bit 25 and Blend Function Select in bit 24.D<22 = BLT Source Buffer B, State Set 0 only
<-HangingPara_noSA > 0 Disable Buffer B (enable Buffer A) <-HangingPara_noSA > 1 Enable Buffer B (disable Buffer A)
D<21:18 = ROP Code, State Set 0 and 1
This field selects the desired boolean ROP (raster operation) as follows:
D<17:14 = Z-Buffering Control, State Set 0 and 1
This field controls the use of the depth planes. Each bit controls a specific
function as follows:
The bits are coded as shown in Table 6-5 for HSR functions (using Z as a depth buffer, State Set 1 only). For WID functions (using Z as a WID extension; State Set 0 or 1), the bits are coded as shown in Table 6-6.
Table 6-5 HSR (Hidden Surface Removal) Functions
---------------------------------------------------------------------------------------------------------------------------------------------------------
Code Z Compare Z Update Application ---------------------------------------------------------------------------------------------------------------------------------------------------------
0000 No No Don't write Z
01c0 No Yes Write Z, no HSR
10c0 Yes No Write to RGB only, if Z is in front
11c0 Yes Yes Write RGB and Z, if Z is in front
---------------------------------------------------------------------------------------------------------------------------------------------------------
Table 6-6 WID Extension Functions
-----------------------------------
Code WID Ext Clip WID Ext Replace -----------------------------------
0010 No No
1101 Yes Yes
1111 Yes Yes
0011 Yes No
0110 No Yes
0111 Yes Yes
-----------------------------------
D<13:12 = Stereo Control, State Set 0 and 1
Bit 12 defines the current window application as stereo (1) or "mono" (0).
Applications that do not know how to take advantage of the 24-bit stereo mode
(stereo bit set in the Frame Buffer Width register) should clear bit 12 (this
should be the window system default initialization). Bit 13 (the left/right bit) is
ignored in this case. Applications that know how to use the 24-bit stereo mode
should set bit 12 and then use bit 13 to specify the desired half of the frame
buffer (0 for left or 1 for right).
If bit 12 is set to "mono" AND the Frame Buffer Width register is set to stereo,
then LD duplicates all writes to the frame buffer. The first write goes to (X, Y)
in the left buffer; the second to (X, Y) in the right buffer. Bit 13 of this register
is ignored.
If bit 12 is set to "stereo" AND the Frame Buffer Width register is set to stereo,
then LD writes once, to (X, Y) in the buffer indicated by bit 13.
The bits are coded as follows:
<-HangingPara_noSA > x0 Mono <-HangingPara_noSA > x1 Stereo <-HangingPara_noSA > 0x Left <-HangingPara_noSA > 1x Right
D<11:5 = Plane Group Enable, State Set 0 and 1
This field is used by the window system to enable and disable individual plane
groups. A pixel in a particular plane is updated only if that plane group is
enabled AND the write mask is "1". This behavior is modified for fast clear
windows and is discussed separately. Each bit (0 = disable, 1 = enable) controls
a specific plane as follows:
D<4 = Force Current WID, State Set 0 and 1
<-HangingPara_noSA > 0 Do not force Current Window ID. <-HangingPara_noSA > 1 The contents of the Current Window ID plane (see page 6-39) replaces the contents of the frame buffer on every write. The final write to the WID planes is still controlled by the plane mask and the window plane group enable bit.
D<3:1 = Fast Clear Plane Select, State Set 0 and 1
Identifies which (if any) Fast Clear Planes are used by the current window. In
both state sets, this field specifies which Fast Clear Plane (if any) should be
tested to determine if the current read pixel is valid. Coded as follows:
D<0 = Buffer B Select, State Set 0 and 1
Double buffer control for the RGB planes. Set to 1 to select Buffer B as the
target for all read, write and read - modify - write accesses on the frame buffer.
For the Block Copy operation, however, bit 22 (Blt Source Buffer B), provides
an independent selection of the source buffer. This allows Block copy
operations between Buffer A and Buffer B. Bit 22 is present only in State Set 0.
There are two Stencil Access registers:
0x040 0020 for State Set 0
0x140 0020 for State Set 1
Direct Port only: State Set 0 or 1; Read and Write
This register specifies the frame buffer pixel data during a Stencil mode access. The stencil bits that are set to 1 use the foreground color. During a Fill, data in these registers is written to the frame buffer for every pixel. Note that there is only one physical register. The format of the data in this register depends on the selected plane group as shown above.
D<31:24 = Overlay
Specifies the overlay pixel value.
D<23:16 = Blue
Specifies the blue pixel value.
D<15:8 = Green
Specifies the green pixel value.
D<7:0 = Red
Specifies the red pixel value.
D<23:0 = Depth
Specifies the depth (Z) of the pixel.
D<15:10 = Fast Clear
Each bit specifies a fast clear plane: bit 10 specifies plane 0, bit 11 specifies
plane 1, and so on.
D<9:6 = Overlay Window ID Planes
Specifies the Overlay Window ID plane.
D<5:0 = Image Window ID Planes
Specifies the Image Window ID plane.
0x040 0024 for State Set 0
0x140 0024 for State Set 1
Direct Port only: State Set 0 or 1; Read and Write
This register specifies the frame buffer pixel data during a Stencil mode access. The stencil bits that are set to 0 use the background color if the Transparency flag = 0.
D<31:24 = Overlay
Specifies the overlay pixel value.
D<23:16 = Blue
Specifies the blue pixel value.
D<15:8 = Green
Specifies the green pixel value.
D<7:0 = Red
Specifies the red pixel value.
D<23:0 = Depth
Specifies the depth (Z) of the pixel.
D<15:10 = Fast Clear
Specifies the fast clear plane.
D<9:6 = Overlay Window ID Plane
Specifies the Overlay Window ID plane.
D<5:0 = Image Window ID Plane
Specifies the Image Window ID plane.
The Block Copy function copies a source rectangle to a destination rectangle. This function uses all of the State Set 0 registers used for pixel access plus the following three registers:
Note that the software does not normally use these registers. They are used by the LeoCommand chip.
0x040 0028
Direct Port only: State Set 0 only; Read or Write
Specifies the initial frame buffer source address for a rectangle copy operation. Reading this address after a copy returns an indeterminate result.
D<31:30 = Source Group
Specifies the copy source plane group. Code as follows (note that the first bit
shown is the Byte Mode bit from the "Copy/Scroll/Fill Destination Address"
register on page 6-25):
D<25:16 = Source Y
Specifies the Y source address (10 bits). Valid values are in the range 0 through
1023.
D<7:0 = Source X
Specifies the X source address (8 bits). Valid values are in the range 0 through
255. Note that the X source address is equal to the integer value of the (actual
X source address)/5.
0x040 0030
Direct Port only: State Set 0 only; Read or Write
Specifies the size for a rectangle copy or fill operation, and the direction for a copy operation. Reading this address after a copy returns an indeterminate result.
D<31 = Copy Direction
Specifies the copy direction as follows:
For fills, set to 0.
D<7:0 = Size
Specifies the x size (8 bits) of the block. Valid values are in the range 0 through
255. Note that the x size is equal to the integer value of the (actual x size)/5.
0x040 002C
Direct Port only: State Set 0 only; Read or Write
Specifies the initial frame buffer destination address for a rectangle copy operation. Reading this address after a copy returns an indeterminate result. Note that the LeoCommand chip maps the two different SBus addresses (for Copy and Fill) to the same address on the LeoDraw chip.
D<31 = Byte Mode
Specifies Byte or Pixel mode. Pixel mode must be used for fills.
D<30:29 = Destination Group
Specifies the destination plane group for Pixel mode. Byte mode, which always
uses the Image plane group, ignores this field (the image write mask
determines the destination).
D<28 = Ext
Specifies the destination width extension. The destination width is 1 less than
Size.
D<25:16 = Destination Y
Specifies the Y destination address (10 bits). Valid values are in the range 0
through 1023.
D<7:0 = Destination X
Specifies the X destination address (8 bits). Valid values are in the range 0
through 255. Note that the X destination address is equal to the integer value of
the (actual X destination address)/5.
There are two viewport clipping registers:
0x040 0010 for State Set 0
0x140 0010 for State Set 1
Direct Port: State Set 0 or 1; Read and Write
Accelerator Port: State Set 1 only; Write only
Specifies the viewport top and left (inclusive) boundaries: the coordinates of the top left corner. The LeoDraw chip clips the pixel if Y < top or if X < left. Note that Y = 0 is the top of the screen and X = 0 is the left side of the screen.
D<25:16 = Top Boundary
Specifies the top boundary of the clip area. Note that the Y values are 10 bits.
D<10:0 = Left Boundary
Specifies the left boundary of the clip area.
0x040 0014 for State Set 0
0x140 0014 for State Set 1
Direct Port: State Set 0 or 1; Read and Write
Accelerator Port: State Set 1 only; Write only
Specifies the viewport bottom and right (inclusive) boundaries: the coordinates of the bottom right corner. The LeoDraw chip clips the pixel if X right or if Y > bottom. Note that Y = 0 is the top of the screen and X = 0 is the left side of the screen.
D<25:16 = Bottom Boundary
Specifies the bottom boundary of the clip area. Note that the Y values are 10
bits.
D<10:0 = Right Boundary
Specifies the right boundary of the clip area.
There are six Pick registers:
Clear Pick Hit
Pick ID Register[4,0]
Pick Minimum Bound
Pick Maximum Bound
Pick Front Bound
Pick Back Bound
0x140 0048
Direct Port only: State Set 1; Write (Strobe)
Writing to this location resets the pick hit output and allows LeoDraw chip to update the PID registers. This is a "strobe" location - the data is a "don't care."
0x140 00E0 Pick ID Register 0
0x140 00E4 Pick ID Register 1
0x140 00E8 Pick ID Register 2
0x140 00EC Pick ID Register 3
0x140 00F0 Pick ID Register 4
Direct Port: State Set 1 only; Read and Write
Accelerator Port: Set 1 only; Write only
Sets the current Pick IDs (five 32-bit registers). These registers are written through the accelerator port. If picking is enabled, LD ensures that the PID registers cannot be updated once a pick-hit is detected. Furthermore, it also ensures that the registers are not updated until all the pixels for any prior draw command have been rendered without picking. The host code can not update the PIDs via the direct port during picking, but it can render pixels that are subject to picking via the direct port.
0x140 0018
Direct Port: State Set 1 only; Read and Write
Accelerator Port: State Set 1 only; Write only
Specifies the pick aperture top and left (inclusive) boundaries. The LeoDraw chip does not generate a pick hit if Y < top or if X < left.
D<25:16 = Top Boundary
Specifies the top boundary of the pick aperture.
D<10:0 = Left Boundary
Specifies the left boundary of the pick aperture.
0x140 001C
Direct Port: State Set 1 only; Read and Write
Accelerator Port: State Set 1 only; Write only
Specifies the pick aperture bottom and right (inclusive) boundaries: the coordinates of the bottom right corner. The LeoDraw chip does not generate a pick hit if X right or if Y > bottom. Note that Y = 0 is the top of the screen and X = 0 is the left side of the screen.
D<25:16 = Bottom Boundary
Specifies the bottom boundary of the pick aperture. Note that the Y values are
10 bits.
D<10:0 = Right Boundary
Specifies the right boundary of the pick aperture.
0x140 00B0
Direct Port: State Set 1 only; Read and Write
Accelerator Port: State Set 1 only; Write only
Specifies the pick aperture front (inclusive) boundary. The LeoDraw chip does not generate a pick hit if Z < front and the Pick CSR 3-D field is set. Note that Z = 0 is nearest the viewer.
D<23:0 = Front Boundary
Specifies the front boundary of the pick aperture.
0x140 00B4
Direct Port: State Set 1 only; Read and Write
Accelerator Port: State Set 1 only; Write only
Specifies the pick aperture back (inclusive) boundary. The LeoDraw chip does not generate a pick hit if Z back and the Pick CSR 3-D field is set. Note that Z = 0 is nearest the viewer.
D<23:0 = Back Boundary
Specifies the back boundary of the pick aperture.
There are five Video Control registers:
Screen Start Address Left (Even)
Screen Start Address Right (Odd)
Screen Offset Left (Even)
Screen Offset Right (Odd)
Video Counter
0x040 1000
Direct Port only: Global; Read and Write
Specifies the address of the first displayed pixel for the left (Stereo Mode), even (Interlaced Mode), or non - stereo non - interlaced frame buffer. This address is used to initialize the video address counter. The counter is incremented by the contents of the Screen Offset Left (Even) register after every transfer cycle.
D<17:0 = Linear Start Address
Specifies the linear start address of the first displayed pixel for the left, even, or
non - stereo non - interlaced frame buffer.
0x040 1004
Direct Port only: Global; Read and Write
Specifies the address of the first displayed pixel in the right (Stereo Mode) or odd (Interlaced Mode) frame buffer. This register is used only in Interlaced or Stereo Modes. This address is used to initialize the video address counter. The counter is incremented by the contents of the Screen Offset Right (Odd) register after every transfer cycle.
D<17:0 = Linear Start Address
Specifies the linear start address of the first displayed pixel for the right or odd
frame buffer.
0x040 1008
Direct Port only: Global; Read and Write
Specifies the value that is added to the contents of the video counter after every transfer cycle of a left or even frame.
D<17:0 = Linear Address
Specifies the linear address that is added to the contents of the video counter
after every transfer cycle of a left or even frame.
0x040 100C
Direct Port only: Global; Read and Write
Specifies the value that is added to the contents of the video counter after every transfer cycle of a right or odd frame.
D<17:0 = Linear Address
Specifies the linear address that is added to the contents of the video counter
after every transfer cycle of a right or odd frame.
0x040 1010
Direct Port only: Global; Read only; reset on every vertical retrace
Specifies the address of the next transfer cycle. It is loaded by the video refresh logic on LeoDraw. It is readable for diagnostic purposes only.
D<17:0 = Linear Address
Specifies the address of the next transfer cycle. It is loaded by the video refresh
logic on LeoDraw. It is readable for diagnostic purposes only.
Screen Door Transparency is specified using 16 16-bit (8 words) Screen Door Column registers.
0x140 00C0 Column 1 and 0
0x140 00C4 Column 3 and 2
0x140 00C8 Column 5 and 4
0x140 00CC Column 7 and 6
0x140 00D0 Column 9 and 8
0x140 00D4 Column 11 and 10
0x140 00D8 Column 13 and 12
0x140 00DC Column 15 and 14
Direct Port: State Set 1 only; Read and Write
Accelerator Port; State Set 1 only; Write only
A set of sixteen 16-bit registers that define the 16 \xb4 16 screen door transparency pattern. Each register defines one 16 pixel column of the pattern. If the pattern bit is one, the object is solid (visible) at that pixel; if the pattern bit is zero, the object is transparent and the pixel is not drawn. Note that Hawk uses a 20 \xb4 16 screen door.
Address offset "nn" is the column number, ranging from 0 to 7 (decimal).
The column number is equal to 2 \xb4 nn for even columns and 2 \xb4 nn + 1 for odd columns, where nn (the address offset) ranges from 0 to 7 decimal.
D<31:16 = Column Odd
Rows 15 through 0 are specified by bits 31 through 16.
D<15:0 = Column Even
Rows 15 through 0 are specified by bits 15 through 0.
Fast Clear operations are specified using the following two registers.
0x140 004C
Direct Port: State Set 1 only; Read and Write
Accelerator Port: State Set 1 only; Write only
The data in this register is written to the fast clear planes during VRAM flash write memory cycles. The fast clear plane mask specifies which bits are actually written.
D<15:10 = Fast Clear
This 6-bit field is written to the fast clear planes during VRAM flash write
memory cycles. The fast clear plane mask (see "Window Write Mask" on
page 6-43) specifies which bits are actually written.
0x040 0080
0x140 0080
Direct Port: State Set 0 and 1; Read and Write
Accelerator Port: State Set 1 only; Write only
Specifies the window background color (RGBO) used in LD operations. A background of all 1's is used for the Z plane. The Window plane group is always valid and never needs a background.
This value is used in two ways:
D<31:24 = Overlay
Specifies the overlay pixel value.
D<23:16 = Blue
Specifies the blue pixel value.
D<15:8 = Green
Specifies the green pixel value.
D<7:0 = Red
Specifies the red pixel value.
There are two Window ID registers:
0x040 0004 for State Set 0
0x140 0004 for State Set 1
Direct Port: State Set 0 and 1; Read and Write
Accelerator Port: State Set 1 only; Write only
Specifies the Current Window ID code. This code is forced into the WID planes if the Force Current WID attribute is enabled (bit 4 of "LD Attribute" register, see page 6-15). This code is compared to any unmasked WID planes if WID clipping is enabled (see "WID Clip Mask" on page 6-40).
D<9:4 = PWID
Specifies the PWID (P Window ID ) code. When the QWID code is zero, the
PWID code in the WID planes selects one of 64 locations in the PWID Look Up
Table (LUT). See "WID Look Up Table and Shadow" on page 7-17.
D<3:0 = QWID
Specifies the QWID (Q Window ID) code. When not zero, the QWID code in
the WID planes selects one of 15 locations in the QWID Look Up Table (LUT).
See "WID Look Up Table and Shadow" on page 7-17.
0x040 000C for State Set 0
0x140 000C for State Set 1
Direct Port: State Set 0 and 1; Read and Write
Accelerator Port: State Set 1 only; Write only
Specifies the current WID clip mask. Setting the bits in the WID mask enables the corresponding bits in the Current WID register during the WID clip compare; clear bits masks them. To defeat WID clipping, clear all of the mask bits.
D<9:4> = P Window Clip Mask
Specifies the P Window ID clip mask.
D<3:0> = Q Window Clip Mask
Specifies the Q Window ID clip mask.
The 24 frame buffer Z planes have two major and mutually exclusive functions:
0x040 008C for State Set 0
0x140 008C for State Set 1
Direct Port: State Set 0 and 1; Read and Write
Accelerator Port: State Set 1 only; Write only
Specifies a constant that can be written to the depth (Z) planes. Useful as a WID extension for window clipping. Also useful for parallel pixel mode writes (plane group = 11) of Z and RGBO (State Set 1 only).
D<23:0 = z
Specifies a constant Z source that can be written to the depth planes.
There are two Write Mask registers:
0x040 0084 for State Set 0
0x140 0084 for State Set 1
Direct Port: State Set 0 or 1; Read and Write
Accelerator Port: State Set 1 only; Write only
Per plane write mask for RGBO planes. Note that there is no separate byte mask for "byte mode" pixel writes. LeoDraw replicates the byte in all four bytes of the image plane group. The image write mask is used to determine which byte gets written to the frame buffer.
For each of the eight bits in each mask, 0 = disable write, 1 = enable write.
D<31:24 = Overlay Mask
Specifies the overlay pixel mask.
D<23:16 = Blue Mask
Specifies the blue pixel mask.
D<15:8 = Green Mask
Specifies the green pixel mask.
D<7:0 = Red Mask
Specifies the red pixel mask.
0x040 0008 for State Set 0
0x140 0008 for State Set 1
Direct Port: State Set 0 or 1; Read and Write
Accelerator Port: State Set 1 only; Write only
Per plane write mask for Fast Clear, Overlay Window, and Image Window planes.
For each of the bits in each mask, 0 = disable write, 1 = enable write.
D<15:10 = Fast Clear Mask
Specifies the Fast Clear mask.
D<9:4> = Image Window Plane Mask
Specifies the Image Window Plane mask.
D<3:0> = Overlay Window Plane Mask
Specifies the Overlay Window Plane mask.
There are two Color/Alpha Registers:
0x140 0050
Direct Port: State Set 1 only; Read and Write
Accelerator Port: State Set 1 only; Write only
Specifies a constant alpha source that may be substituted for the Antialias Filter alpha.
D<8:0 = Constant Alpha
Specifies a constant alpha source between 0 and 1 that may be substituted for
the AA Filter alpha. The format of the constant is "w.ff", where w may be zero
or one. If w=1 then "ff" must be zero. The value of w is specified in bit 8, and
the value of ff is specified in bits 7 through 0.
0x140 00BC
Direct Port: State Set 1 only; Read and Write
Accelerator Port: State Set 1 only; Write only
Specifies a constant color source that may be substituted for the color values generated by the DDA unit. Substitution is enabled by setting the Force Color Enable bit in the "LD Attribute" register (see page 6-15).
D<23:16 = Blue
Specifies the blue pixel color.
D<15:8 = Green
Specifies the green pixel color.
D<7:0 = Red
Specifies the red pixel color.
Depth Cueing operations are performed using the following six registers:
0x140 00A0
Direct Port: State Set 1 only; Read and Write
Accelerator Port: State Set 1 only; Write only
Specifies the Z - front value for use in depth cueing.
0x140 00A4
Direct Port: State Set 1 only; Read and Write
Accelerator Port: State Set 1 only; Write only
Specifies the Z - back value for use in depth cueing.
0x140 00A8
Direct Port: State Set 1 only; Read and Write
Accelerator Port: State Set 1 only; Write only
Specifies the front and back scale factors for use in depth cueing. The scale values are 9 bits and are in the range 0 to 1.0. The format of each value is "w.ff", where w may be zero or one. If w=1 then "ff" must be zero. The value of w is specified in the first bit of the field, and the value of ff is specified in remaining bits.
0x140 00AC
Direct Port: State Set 1 only; Read and Write
Accelerator Port: State Set 1 only; Write only
Specifies the Z - scale factor for use in depth cueing. It consists of an 9-bit mantissa and a 6-bit exponent. Both the mantissa and exponent are in two's complement representation. The number represented by the scale is = (mantissa/128) * 2 (exponent)
0x140 00B8
Direct Port: State Set 1 only; Read and Write
Accelerator Port: State Set 1 only; Write only
Specifies the fade color for use in depth cueing. Phigs+ depth cueing is
implemented as follows:
C = S Ci + (1 - S) Cd
Where:
C = Component of depth cued color
Ci = Component of the input color
Cd = Component of the depth cue fade color
S = Depth cue scale factor that is computed in LeoDraw as follows:
If Z is in front of Z - front, then S= front scale
If Z is behind Z - back, then S= back scale
If Z is between Z - front, and Z - back then
S= back scale + (Z - Zback) * Zscale
D<23:16 = Blue
Specifies the blue pixel fade color.
D<15:8 = Green
Specifies the green pixel fade color.
D<7:0 = Red
Specifies the red pixel fade color.
The tables in this section describe the pixel operations for the following plane groups:
Fast Clear Planes, Table 6-7
Window ID Planes, Table 6-8
Image (ORGB) Planes, Table 6-9
Depth Planes, Table 6-10
These tables show the conditions that are checked before a pixel is written to the frame buffer.
The following paragraphs define the information shown in the various columns of the tables.
A "1" indicates that the pixel is in the viewport as defined by the "View Clip Minimum Bound" and "View Clip Maximum Bound" registers.
A "1" indicates a Pick Control code (bits 31:29 of "LD Attribute" register) of 10x - enable picking and do not render while picking.
For each bit that is 1 in the "WID Clip Mask" register, the bit in FB Data In = "Current Window ID" data register bit.
H is bit 17 (Hidden Surface Removal enable) of the "LD Attribute" register.
X is bit 14 (WID extension clip enable) of the "LD Attribute" register.
For X = 0, H = 0: hsr.win = 1
For X = 0, H = 1: if (Znew <= Zold) hsr.win = 1; else hsr.win = 0
For X = 1, H = 0: if (Znew == Zold) hsr.win == 1; else hsr.win = 0
For X = 1, H = 1: if (Znew == Zold) hsr.win == 1; else hsr.win = 0
This is bit 10 (Fast Clear Enable) of "LD Attribute" register.
A "1" indicates that the I and D planes are valid.
I = Image (ORGB) planes, Direct Port write or read
D = Depth (Z) plane, Direct Port write or read
W = Window (FC + WID) planes, Direct Port write or read
ID = Image + Depth, Accelerator Port write only or Direct Port write only
The element "Bit M (m, Side 1, Side 0)" means that for each bit in mask m: if m = 0, select Side 0 bit; if m = 1, select Side 1 bit.
"FB Data In" means that data written out to the frame buffer is the same as data read in from the frame buffer. The pixel is not modified.
The first line of Table 6-9 means that for a window access, data is never written out to the frame buffer ORGB planes (Data Out to FB = FB Data In).
The second line of Table 6-9 means that (for an I, D, or ID access) if the pixel is not in the viewport, the pixel is not written (Data Out to FB = FB Data In).
The eighth line of Table 6-9 means that for an I or ID pixel access, if all the conditions to the left of the vertical line are met, then: the data read in from the frame buffer is passed to the ROP and blend units unchanged AND data written out to the frame buffer is the output of the ROP/Bland Unit (under control of the Write Mask).
Table 6-7 Fast Clear Planes
----------------------------------------------------------------------------------------------------------------------------
Pix In Pick WID HSR Win Screen Fast Access Data Out to Frame Buffer Viewport without Match Door Clear Mode Render Write Enable Enable ----------------------------------------------------------------------------------------------------------------------------
1 x x x x x W Bit M (Window Mask, Pipe data,
FB Data In)
0 x x x x x W FB Data In
0 x x x x x I, D, ID FB Data In
x 1 x x x x I, D, ID FB Data In
x x 0 x x x I, D, ID FB Data In
x x x 0 x x I, D, ID FB Data In
x x x x 0 x I, D, ID FB Data In
1 0 1 1 1 0 I, D, ID FB Data In
1 0 1 1 1 1 I, D, ID Bit M (Decode FC Plane, 0x3F, FB
Data In)
----------------------------------------------------------------------------------------------------------------------------
Table 6-8 Window ID Planes
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Pix In Pick WID HSR Win Screen Window Access Data Out to Frame Buffer Viewport without Match Door Enable Mode Render Write Enable -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
x x x x x 0 W FB Data In
0 x x x x 1 W FB Data In
1 x x x x 1 W Bit M (Window Mask, Pipe Data,
FB Data In)
0 x x x x x I, D, ID FB Data In
x 1 x x x x I, D, ID FB Data In
x x 0 x x x I, D, ID FB Data In
x x x 0 x x I, D, ID FB Data In
x x x x 0 x I, D, ID FB Data In
x x x x x 0 I, D, ID FB Data In
1 0 1 1 1 1 I, D, ID Bit M (Window Mask, Pipe Data,
FB Data In)
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Table 6-9 Image (ORGB) Planes
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Pix Pick WID HSR Screen Image Fast Fast Access ROP Data Out to In without Match Win Door Enb Clear Clear Mode or Frame Buffer View Render Write Enb Bit Blend Port Enable Source (SRC) -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
x x x x x x x x W x FB Data In
0 x x x x x x x I, D, ID, x FB Data In
x 1 x x x x x x I, D, ID x FB Data In
x x 0 x x x x x I, D, ID x FB Data In
x x x 0 x x x x I, D, ID x FB Data In
x x x x 0 x x x I, D, ID x FB Data In
x x x x x 0 x x I, D, ID x FB Data In
1 0 1 1 1 1 0 x I, ID FB D In Bit M (Mask,
ROP/Blend Out, FB
Data In)
1 0 1 1 1 1 1 1 I, ID FB D In Bit M (Mask,
ROP/Blend Out, FB
Data In)
1 0 1 1 1 1 1 0 I, ID BG Bit M (Mask,
ROP/Blend Out, BG )
1 0 1 1 1 1 0 x D x FB Data In
1 0 1 1 1 1 1 1 D x FB Data In
1 0 1 1 1 1 1 0 D x BG
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Table 6-10 Depth Planes
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
Pix In Pick WID HSR Screen Z Z Write Fast Fast Access Data Out to Viewport without Match Win Door Group Enable Clear Clear Mode Frame Buffer Render Write Enable Enable Bit Enable -----------------------------------------------------------------------------------------------------------------------------------------------------------------------
x x x x x x x x x W FB Data In
0 x x x x x x x x I, D, ID FB Data In
x 1 x x x x x x x I, D, ID FB Data In
x x 0 x x x x x x I, D, ID FB Data In
x x x 0 x x x x x I, D, ID FB Data In
x x x x 0 x x x x I, D, ID FB Data In
x x x x x 0 x x x I, D, ID FB Data In
1 0 1 1 1 1 1 0 x ID, D Znew
1 0 1 1 1 1 1 1 1 ID, D Znew
1 0 1 1 1 1 1 1 0 ID, D Znew
1 0 1 1 1 1 0 0 x ID, D FB Data In
1 0 1 1 1 1 0 1 1 ID, D FB Data In
1 0 1 1 1 1 0 1 0 ID, D 0xFF FFFF
1 0 1 1 1 1 x 0 x I FB Data In
1 0 1 1 1 1 x 1 1 I FB Data In
1 0 1 1 1 1 x 1 0 I 0xFF FFFF
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