4 Address Space Detail





This chapter describes the basic structure of the address space. The following chapters define the data formats.

The Leo board is installed in SBus slots of the Host. The size of the SBus address space is 256 MBytes (a 28-bit address). However, SBus expansion boards, such as Leo, ignore address bits 27 through 25. The size of the Leo Address Map is therefore 32 MBytes (225).

Some of the SBus address bits of the Leo address space define specific conditions. The bits that are defined in the same way for the register and the frame buffer address space are shown below.

A<24 = State Set

Set to 0 to select State Set 0. Set to 1 to select State Set 1.

A<23 = Select Frame Buffer

Set to 1 to select the Frame Buffer Address Space. Set to 0 to select the Register Address Space.

Note that the hardware supports two executions threads - one for State Set 0 and one for State Set 1. The hardware maintains a separate context for each of these threads. This allows two processes to access the hardware without a separate hardware context switch.

The address map (shown in Figure 4-1) is divided into four 2 MBytes parts:

    State Set 0 Registers

    State Set 0 Frame Buffer

    State Set 1 Registers

    State Set 1 Frame Buffer

Note that the two register spaces are divided into four parts: the Boot PROM chip, the LeoCommand chip, the LeoDraw chip, and the LeoCross (or RAMDAC) chip. Address bits 22 and 21 identify the chip type.

There are two sets of registers in LeoDraw and LeoCommand, one for State Set 0 and one for State Set 1. The State Set bit is used to differentiate access to those two sets of registers along with determining which set is to be used for the Frame Buffer accesses and Stencil operations. For example, when accessing the Frame Buffer, the appropriate register set, State Set 0 or 1, is used as specified by the State Set bit in the address.

State Set 0 and State Set 1 are also known and referred to as the Direct Port State Set and the Accelerator Port State Set, respectively.

The PROM and the LeoCross Registers are repeated in the address space to simplify hardware address decoding. They don't have separate state set registers.

The LeoFloat chips and their associated SRAM memories do not appear in the address space and hence are not directly addressable. The LeoFloat registers and their SRAM memory are accessed indirectly through the LeoCommand Registers.

The address space has holes. If the software writes these holes, the board acknowledges the bus cycle but ignores the transfer. If the software reads these holes, the board acknowledges the bus cycle, but the value returned is random.

If the software writes a valid address, but the location is read only, the board acknowledges the bus cycle but ignores the transfer.

4.1 Notation

The figures and tables in this chapter use the following letters to indicate what software can access the specified address range:

<-FigureBoxWide > <-FigureBoxWide >

    Figure 4-1 Leo Address Map

    K = Kernel. The kernel software includes the device driver and the segment driver. Diagnostic software is also classified as kernel software.

    L = LeoSPARC. The LeoSPARC process traverses the vertex list.

    N = Native. The native graphics library, which is XGL.

    W = Window. This is the window process.

4.2 Frame Buffer Address Space

Reading and writing the frame buffer consists of reading data from or writing data to the address of each desired pixel location in the frame buffer. This section provides an overview and then describes the frame buffer address format and data formats for Pixel Access Mode, Byte Access Mode, and Stencil Access Mode. It also describes frame buffer to display mapping.

4.2.1 Overview

A frame buffer address is related to a pixel location on the screen using an 11-bit X and 10-bit Y screen coordinate system. The origin is in the upper left corner, with X and Y increasing to the right and down, respectively. The coordinates describing a pixel location are integers.

The frame buffer consumes 8 MBytes in the SBus address space using address bits A22 - A0. The frame buffer is mapped twice, once for each State Set as shown in Table 4-1.

    Table 4-1 Frame Buffer State Set 0 and 1

----------------------------------------------------------
Address Size Register Name Access ----------------------------------------------------------
                                                     
Ox0800000  8 Mbyte  Frame Buffer State Set 0, start  R/W
                                                     
Ox0FFFFFF           Frame Buffer State Set 0, end    
                                                     
Ox1800000  8 Mbyte  Frame Buffer State Set 1, start  R/W
                                                     
Ox1FFFFFF           Frame Buffer State Set 1, end    

----------------------------------------------------------

To conserve the size of the address space used for the frame buffer, the various access modes for the frame buffer and the frame buffer plane groups are all mapped through the same address space. The contents of the Frame Buffer Address Space Register (see page 5-31) determine the access modes and the plane groups being accessed (there is a separate Frame Buffer Address Space Register for each state set).

There are three access modes to the frame buffer: Pixel, Byte, and Stencil. The plane groups available for Pixel and Stencil Access Modes are the Image, Depth, and Window planes. For Byte Access Modes, the plane groups available are the Overlay, Blue, Green, and Red partitions of the Image buffer.

The 4-bit Access Code in bits 3-0 of the Frame Buffer Address Space register selects the access mode and plane group as shown in Table 4-2. Note that the Pixel Access Mode only support 4-byte access. The Stencil and Byte Access Modes support 1-byte, 2-byte, and 4-byte access. If an illegal access is done, the SBus transaction is completed, however, the results are not specified and the Slave Illegal Address bit in the LeoCommand SBus Status Register (see page 5-7) is set.

    Table 4-2 Frame Buffer Address Space States

--------------------------------------------------------
Access Access Buffer 4-Byte 2-Byte 1-Byte Code Mode Access Access Access --------------------------------------------------------
                                                    
0000     Pixel    Image          OBGR      Illegal  Illegal
                                                    
0001     Pixel    Depth          Z         Illegal  Illegal
                                                    
0010     Pixel    Window         W         Illegal  Illegal
                                                    
0011     Pixel    Image + Depth  OBGR + Z  Illegal  Illegal
                                                    
0100     Stencil  Image          SSSS      SSxx     Sxxx
                                                    
0101     Stencil  Depth          SSSS      SSxx     Sxxx
                                                    
0110     Stencil  Window         SSSS      SSxx     Sxxx
                                                    
0111     Stencil  N/A            Illegal   Illegal  Illegal
                                                    
1000     Byte     Image - O      OOOO      OOxx     Oxxx
                                                    
1001     Byte     Image - B      BBBB      BBxx     Bxxx
                                                    
1010     Byte     Image - G      GGGG      GGxx     Gxxx
                                                    
1011     Byte     Image - R      RRRR      RRxx     Rxxx
                                                    
11XX     N/A      N/A            Illegal   Illegal  Illegal

--------------------------------------------------------

4.2.2 Pixel Access Mode

Pixel Access Mode is used to read and write one pixel per transfer where a pixel can be up to 32 planes occupying 4 bytes. The Pixel Access Mode address and data formats are shown below.

4.2.2.1 Address Format.

4.2.2.2 Data Formats

4.2.3 Stencil Access Mode

Stencil Access Mode is used to write 1 to 32 pixels per transfer. It is used primarily for accelerated text generation. Reads are not supported in Stencil Mode. The address format is the same as the Pixel Access Mode. The Stencil Access Mode address and data formats are shown below.

4.2.3.1 Address Format

4.2.3.2 Data Formats

The data formats are shown as seen on the SBus. The Stencil operation also uses the "Stencil Mask" register (see page 5-33) and the "Stencil Transparent Enable" register (see page 5-34). The pixel is modified according to the corresponding bit locations in the Stencil Mask and the Stencil Data (in the SBus transfer) and the Stencil Transparent Enable flag as shown in Table 4-3.

    Table 4-3 Pixel Modification

---------------------------------------------------------------------
Stencil Mask Stencil Data Transparent Action on Pixel Enable Flag ---------------------------------------------------------------------
                                                
0              X             X                  Pixel unmodified
                                                
1              0             1                  Pixel unmodified
                                                
1              0             0                  Write Background Color
                                                
1              1             X                  Write Foreground Color

---------------------------------------------------------------------

4.2.4 Byte Access Mode

Byte Access Mode is used to read and write 1, 2, or 4 pixels per transfer. It is used to access the Overlay, Blue, Green, and Red partitions of the Image Buffer as independent 8-bit buffers. Each byte represents one pixel. The Byte Access Mode address and data formats are shown below.

4.2.4.1 Address Format

4.2.4.2 Data Formats.

The data formats are shown as seen on the SBus.

4.2.5 Frame Buffer to Display Mapping

The frame buffer supports multiple resolutions. The highest resolution requires 1280 \xb4 1024 pixels. The address space of the frame buffer is 2048 \xb4 1024 pixels. Figure 4-2 shows the mapping of the various display resolutions in the frame buffer address space.

The frame buffer address space has holes. If the resolution is 1280 \xb4 1024, for example, the address range 1280 < X Address < 2047 is bogus. The software should not access these holes.

    Figure 4-2 Frame Buffer to Display Mapping

4.3 Register Address Space

This section describes the register address coding and the address space for each chip type.

4.3.1 Register Address Coding

The SBus address bits that define specific conditions for the register address space are shown below.

A<24 = State Set

<-HangingPara_noSA > 0 Select State Set 0 <-HangingPara_noSA > 1 Select State Set 1

A<23 = Select Frame Buffer
Set to 0 to select the Register Address Space.

A<22:21 = Chip Type A
Coded as follows (along with bit 12) to select the chip type:

--------------------------------
A<22:21'> A<12'> Chip Selected --------------------------------
                   
00         x       Boot PROM
                   
01         x       LeoCommand
                   
10         x       LeoDraw
                   
11         0       LeoCross
                   
11         1       RAMDAC

--------------------------------

A<12 = Chip Type B
Used in conjunction with bits 22 and 21 to select the chip type. When bits 22 and 21 are set to 11, this bit is set to 0 to select the LeoCross chips or to 1 to select the RAMDAC chips.

A<11 = Time Domain
This bit is meaningful only when the chip type is LeoCommand.

<-HangingPara > 0 Select the Leo time domain <-HangingPara_noSA > 1 Select the SBus time domain

A<11:9 = Specific Chip
Coded as shown in Table 4-4 to select a specific LeoDraw chip. For example, code 010 selects LeoDraw chip 2 when LeoDraw is selected by bits 21, and 22. Code 111 specifies a broadcast to all chips for Write Mode and is unspecified for Read Mode.

    Table 4-4 Chip Select Coding of Bits 11 through 9

----------------------------------------------------------
Chip Select Code Write Mode Read Mode A<11:9'> ----------------------------------------------------------
                                            
000                 LeoDraw chip 0          LeoDraw chip 0
                                            
001                 LeoDraw chip 1          LeoDraw chip 1
                                            
010                 LeoDraw chip 2          LeoDraw chip 2
                                            
011                 LeoDraw chip 3          LeoDraw chip 3
                                            
100                 LeoDraw chip 4          LeoDraw chip 4
                                            
101                 Reserved                Reserved
                                            
110                 Reserved                Reserved
                                            
111                 Broadcast to all chips  Unspecified

----------------------------------------------------------

4.3.2 Boot PROM Chip Address Space

The Boot PROM is a read only memory that resides in a 64 KByte segment and is mapped for both state sets. Because address bits A20 - A16 are don't cares, it is repeated several times. The address and data formats are shown below.

The PROM is a byte sized data value. All accesses to it on the SBus result in byte acknowledgment; two and four byte accesses result in dynamic bus sizing.

The Boot PROM Address Space is shown in Table 4-5.

    Table 4-5 Boot PROM Address Space

------------------------------------------------------------------------------
SBus Addr Size Access Function ------------------------------------------------------------------------------
                                
0x000 0000   64 Kbytes  R       Boot PROM, start of first block for State Set 0
                                
0x000 FFFF   ---        R       Boot PROM, end of first block for State Set 0
                                
. . .                           
                                
0x100 0000   64 KBytes  R       Boot PROM, start of first block for State Set 1
                                
0x100 FFFF   ---        R       Boot PROM, end of first block for State Set 1
                                
. . .                           

------------------------------------------------------------------------------

4.3.3 LeoCommand Chip Address Space

The LeoCommand address format is shown below.

A<24 = State Set
LeoCommand registers are available in both states.

<-HangingPara_noSA > 0 Select State Set 0 registers <-HangingPara_noSA > 1 Select State Set 1 registers

A<11 = Time Domain

<-HangingPara_noSA > 0 Select the SBus time domain <-HangingPara_noSA > 1 Select the LeoCommand time domain.

The LeoCommand Registers include registers for the Accelerator Port (State Set 1) and Direct Port (State Set 0). LeoCommand has two clocking regimes, the SBus clock and Leo clock, and hence, the LeoCommand Registers are separated into the SBus clock domain and Leo clock domain. Software need not be concerned with this other than noting the address map differences for registers.

The function of the four major partitions in LeoCommand is shown in Table 4-6. The LeoCommand address map is shown in Table 5-1 through Table 5-4 starting on page 5-2.

    Table 4-6 LeoCommand Partition Functions

--------------------------------------------------------------------
A24 A11 State Set Domain Function --------------------------------------------------------------------
                             
 0   0     Zero       Leo    Control/Status, Stencil, Block Copy/Fill 
                             Registers
                             
 0   1     Zero       SBus   Control/Status Registers
                             
 1   0     One        Leo    Accelerator Port Registers
                             
 1   1     One        SBus   DMA Control Registers

--------------------------------------------------------------------

4.3.4 LeoFloat Chip Address Space

The LeoFloat chip does not appear in the address map. The LeoFloat registers are accessed through the LeoCommand Chip. The LeoCommand chip forwards the read/write opcode and operand data to the LeoFloat chip. For reads, the LeoFloat chip places the values in the LeoFloat output buffer. The LeoCommand chip recovers the register values over the CDBus.

4.3.5 LeoDraw Chip Address Space

The LeoDraw address format is shown below.

A<24 = State Set
LeoDraw registers are available in both states.

<-HangingPara_noSA > 0 Select State Set 0 registers <-HangingPara_noSA > 1 Select State Set 1 registers

A<12 = Global

<-HangingPara_noSA > 0 Access State Set 0 or 1 registers <-HangingPara_noSA > 1 Access Global registers

A<11:9 = Specific Chip
Coded as follows:

<-HangingPara > 000 Access LeoDraw chip 0 <-HangingPara_noSA > 001 Access LeoDraw chip 1 <-HangingPara_noSA > 010 Access LeoDraw chip 2 <-HangingPara_noSA > 011 Access LeoDraw chip 3 <-HangingPara_noSA > 100 Access LeoDraw chip 4 <-HangingPara_noSA > 101 Reserved. LeoCommand takes reads and writes for this code. For writes, it does nothing. For reads, it does nothing on the CDBus, and writes garbage on the SBus. <-HangingPara_noSA > 110 Reserved. See code 101 for details.. <-HangingPara_noSA > 111 Broadcast all LeoDraw chips. Note that for a broadcast read, the first available LeoDraw responds to the read request. If two or more LeoDraws are available, the lowest numbered chip responds (chip 0 takes precedence over chip 1, 2, 3, and 4; chip 1, over 2, 3, and 4; etc.).

Note - All addresses shown here assume access to LeoDraw chip 0 - Specific Chip field = 000. To access LeoDraw 1, 2, 3, or 4, add 0x200, 0x400, 0x600, or 0x800, respectively.

The LeoDraw Registers are separated into Global registers and State Set dependent registers for the Accelerator Port (State Set 1) and Direct Port (State Set 0). The Global registers are mapped into both of the State Sets (the same registers can be accessed by both state sets) when the Global bit is set.

There are five LeoDraw chips. The software may broadcast a write to all five chips or it can also narrowcast data to a specific LeoDraw chip. The Specific Chip field selects the desired chip mode as shown above. The broadcast is useful for setting some attribute that will be constant on all five chips.

Most LD registers contain the same information on all five chips. Thus, in most cases, it is only necessary to read the registers for chip 0. However, write and read the following registers for each chip (they contain unique information): LD Control and Status Register (CSR), LD Interleave, and Clear Pick Hit.

The LeoDraw address map is shown in Table 6-1 through Table 6-3 starting on page 6-2.

4.3.6 CDBus Addressing of LeoDraw Registers

LeoDraw's are actually accessed through the CDBus in the Leo system. The address format shown above was for the SBus. On the CDBus, the LeoDraw Registers have a different address format, which is encoded in the CDBus data packets. The address format is different for the Accelerator and the Direct Port data packets. The Accelerator Port Data Packets are visible to the LeoFloat Microcode. The Direct Port data packets are only visible at the hardware level. The Leo Theory of Operation manual should be referenced for the details, however, the CDBus address formats are shown here for completeness (the address is contained in the CDBus packet headers).

4.3.6.1 CDBus Direct Port Address Format

A<24 = State Set

<-HangingPara_noSA > 0 Select State Set 0 registers <-HangingPara_noSA > 1 Select State Set 1 registers

A<6 = Global

<-HangingPara_noSA > 0 Access State Set 0 or 1 registers <-HangingPara_noSA > 1 Access Global registers

4.3.6.2 CDBus Accelerator Port Address Format

Note - All accesses over the Accelerator Port select State Set 1 registers.

4.3.7 LeoCross Chip Address Space

The LeoCross address format is shown below.

A<24 = State Set
Set to 0 to select State Set 0. Set to 1 to select State Set 1. LeoCross registers are available in both states.

A<13:12 = Page
Specifies the 4,096-byte page. Note that the Video Frame Counter is in page 2, the cursor registers are in page 1, and the other registers are in page 0.

A<5:2 = Register Address
Coded as follows:

<-HangingPara > 0000 LeoCross Address Pointer <-HangingPara_noSA > 0001 LeoCross Control Registers <-HangingPara_noSA > 0010 LeoCross Color Tables <-HangingPara_noSA > 0011 Video Frame Counter <-HangingPara_noSA > 0100 Cursor Address Pointer <-HangingPara_noSA > 0101 Cursor Control and Status Register (CSR) <-HangingPara_noSA > 0110 Shadow Cursor Address <-HangingPara_noSA > 0111 Cursor Functions <-HangingPara_noSA > 1000 RAMDAC Address Pointer <-HangingPara_noSA > 1001 RAMDAC Color Table <-HangingPara_noSA > 1010 RAMDAC Control Register <-HangingPara_noSA > 1011 RAMDAC Mode Register

Note - All addresses shown here assume State Set 0 addresses (A24=0). Recalculate addresses with A24=1 (add 0x100 0000) to access State Set 1 space.

The LeoCross address space is complex in that it is shared by the RAMDAC and LeoCross. Furthermore, access to the RAMDAC and LeoCross internal state is of two types, direct and indirect. The direct type of state is accessed in a single SBus transaction.

The indirect type of access requires two SBus transactions. In the first transaction, the software writes an index value into the RAMDAC, Cursor, or LeoCross Address Pointer register, which points to the register or memory that is to be accessed in a following transaction. In the second transaction, the actual register or memory identified in the address map by that index is accessed. The address pointer is automatically incremented by circuits in the RAMDAC and LeoCross to accommodate access to contiguous memory and register locations. Note that the mapping occurs twice, once for State Set 0 and once for State Set 1.

Table 4-7 shows the SBus address, register size, SBus size, and access type for the LeoCross address space. Note that the Software must format tables using the SBus size.

    Table 4-7 LeoCross and RAMDAC Address Space

-----------------------------------------------------------------------------------------------------------------------------------------------------------------
SBus Register Register Size SBus Size Access Page Address -----------------------------------------------------------------------------------------------------------------------------------------------------------------
                                                                                                                                                              
0x060 0000   LeoCross Address Pointer                            2 Bytes                                                         4 Bytes            Direct    7-9
                                                                                                                                                              
0x060 0004   LeoCross Control Registers (see Table 4-16)         See Table 4-16                                                  See Table 4-16     Indirect  4-26
                                                                                                                                                              
0x060 0008   LeoCross Color Tables (see Table 4-12,              3 Bytes                                                         4 Bytes1           Indirect  4-21
             Table 4-13, Table 4-14, and Table 4-15)                                                                                                          4-23
                                                                                                                                                              4-24
                                                                                                                                                              4-25
                                                                                                                                                              
0x060 0020   RAMDAC Address Pointer                              1 Byte                                                          1 Byte             Direct    7-9
                                                                                                                                                              
0x060 0024   RAMDAC Color Table (see Table 4-10)                 30 or 24 Bits                                                   2 or 4 Bytes       Indirect  4-19
                                                                                                                                                              
0x060 0028   RAMDAC Control Registers (see Table 4-9)            1 Byte                                                          1 Byte2            Indirect  4-19
                                                                                                                                                              
0x060 002C   RAMDAC Mode                                         1 Byte                                                          1 Byte             Direct    8-3
                                                                                                                                                              
0x060 1010   Cursor Address Pointer                              1 Byte                                                          1 Byte             Direct    7-10
                                                                                                                                                              
0x060 1014   Cursor Control and Status Register (CSR)            1 Byte                                                          1 Byte             Direct    7-23
                                                                                                                                                              
0x060 1018   Shadow Cursor Coordinate Address                    23 Bits                                                         3 Bytes            Direct    7-11
                                                                                                                                                              
0x060 101C   Cursor Functions (see Table 4-11)                   4 Bytes                                                         4 Bytes            Indirect  4-20
                                                                                                                                                              
0x060 200C   Video Frame Counter                                 2 Bytes                                                         4 Bytes            Direct    7-51

-----------------------------------------------------------------------------------------------------------------------------------------------------------------

The data transfer details are shown in Table 4-8. Note that the RAMDAC Color Table has two SBus Sizes: 4 Bytes for a 24-bit color size and 2 Bytes for a 30-bit color size.

    Table 4-8 Data Transfer Details

---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Item SBus Size CXBus CXBus Byte SBus Data Format Transfer Transfer Order ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
                                                                                                                                                                   
LeoCross Accesses       4 Bytes    4 Bytes   3, 2, 1, 0                                                                                                            

24-bit Color 4 Bytes 3 Bytes 3, 2, 1

(8 bits per RGB color) 30-bit Color 2 Bytes 2 Bytes 0, 1

(10 bits per RGB color) RAMDAC Mode & 1 Byte 1 Byte 0

Control Registers ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Table 4-9 shows the indirectly accessed registers in the RAMDAC Control Registers. The 8-bit Index value in the table needs to be loaded into the RAMDAC Address Pointer to access the register indicated.

    Table 4-9 RAMDAC Control Registers (Indirect)

-------------------------------------------------------------------------------------
SBus Index Register Name Size Device SBus Size Access Page Address (# loc's) Width -------------------------------------------------------------------------------------
                                                                                     
0x060 0028   0xFF   Reserved, end index       N/A        N/A      N/A        N/A     N/A
              Ø       Ø                                                                       
             0x08   Reserved, start index                                                   
                                                                                     
0x060 0028   0x07   Command Register 3        1          1 Byte   1 Byte     R/W     8-6
                                                                                     
0x060 0028   0x06   Command Register 2        1          1 Byte   1 Byte     R/W     8-5
                                                                                     
0x060 0028   0x05   Reserved                  N/A        N/A      N/A        N/A     N/A
                                                                                     
0x060 0028   0x04   Pixel Mask                1          1 Byte   1 Byte     R/W     8-9
                                                                                     
0x060 0028   0x03   ID                        1          1 Byte   1 Byte     Read    8-9
                                                                                     
0x060 0028   0x02   Sync, Blank, & IPLL Test   1          3 Bits   1 Byte     R/W     8-11
                                                                                     
0x060 0028   0x01   DAC Test                  1          10 Bits  2 Bytes    R/W     8-10
                                                                                     
0x060 0028   0x00   Pixel Test                1          1 Byte   1 byte     Read    8-10

-------------------------------------------------------------------------------------

Table 4-10 shows the indirectly accessed registers in the RAMDAC Color Table. The 8-bit Index value in the table needs to be loaded into the RAMDAC Address Pointer to access the register indicated.

    Table 4-10 RAMDAC Color Table (Indirect)

---------------------------------------------------------------------------------------
SBus Index Register Name Size Device SBus Size Access Page Address Width (# loc's) ---------------------------------------------------------------------------------------
                                                                                        
0x060 0024   0xFF   Color Table 255   256        30 or 24 Bits   2 or 4 Bytes   R/W     8-7
              Ø       Ø                                                                         
             0x00   Color Table 0     256        30 or 24 Bits   2 or 4 Bytes   R/W           

---------------------------------------------------------------------------------------

Table 4-11 shows the indirectly accessed registers in the Cursor section of LeoCross. The 8-bit Index value in the table needs to be loaded into the LeoCross Address Pointer to access the register indicated

    Table 4-11 LeoCross Cursor Functions (Indirect)

--------------------------------------------------------------------------------------
SBus Index Register Name Size Device SBus Access Page Address Width Size (# loc's) --------------------------------------------------------------------------------------
                                                                                      
0x060 101C   0x8F   Reserved                   N/A        N/A      N/A      N/A       N/A
                                                                                             
              Ø       Ø                                                                        
             0x82   Reserved                                                                 
                                                                                      
0x060 101C   0x81   Trap, Bank 1               1          28 Bits  4 Bytes  R/W       7-28
                                                                                      
0x060 101C   0x80   Trap, Bank 0               1          28 Bits  4 Bytes  R/W       7-28
                                                                                      
0x060 101C   0x7F   Reserved                   N/A        N/A      N/A      N/A       N/A
                                                                                             
              Ø       Ø                                                                        
             0x52   Reserved                                                                 
                                                                                      
0x060 101C   0x51   Shadow Cursor Color 1      2          3 Bytes  4 Bytes  R/W       7-11
                                                                                      
0x060 101C   0x50   Shadow Cursor Color 0                                             
                                                                                      
0x060 101C   0x4F   Reserved                   N/A        N/A      N/A      N/A       N/A
                                                                                             
              Ø       Ø                                                                        
             0x41   Reserved                                                                 
                                                                                      
0x060 101C   0x40   Active Cursor Coordinate   1          23 Bits  4 Bytes  Diag R/W  7-12
                    Address                                                                  
                                                                                      
0x060 101C   0x3F   Cursor Color, Row 31       32         4 Bytes  4 Bytes  R/W       7-13
                                                                                             
              Ø       Ø                                                                        
             0x20   Cursor Color, Row  0                                                     
                                                                                      
0x060 101C   0x1F   Cursor Enable, Row  31     32         4 Bytes  4 Bytes  R/W       7-13
                                                                                             
              Ø       Ø                                                                        
                    Cursor Enable, Row  0                                                    
             0x00                                                                            

--------------------------------------------------------------------------------------

.

Table 4-12 shows the indirectly accessed PWID and QWID LUT's and the associated Shadow buffer in the LeoCross Color Tables section of LeoCross. The 16-bit Index value in the table needs to be loaded into the LeoCross Address Pointer to access the register indicated. The WID LUT's are duplicated five times, called bank 4 - 0, in the hardware for timing reasons. There is no reason to load different values into the five banks in normal operation

    Table 4-12 LeoCross Color Tables (Indirect) - WID LUTs

---------------------------------------------------------------------------------
SBus Index Register Name Size Device SBus Size Access Page Address Width (# loc's) ---------------------------------------------------------------------------------
                                                                                 
0x060 0008   0x5FFF  Reserved             N/A        N/A      N/A        N/A     N/A
                                                                                        
              Ø        Ø                                                                  
             0x5850  Reserved                                                           
                                                                                 
0x060 0008   0x584F  Shadow QWID LUT 15   16         10 Bits  2 Bytes    R/W     7-18
                                                                                        
              Ø        Ø                                                                  
                                                                                        
             0x5840  Shadow QWID LUT 0                                                  
                                                                                 
0x060 0008   0x583F  Shadow PWID LUT 63   64         10 Bits  2 Bytes    R/W     7-18
                                                                                        
              Ø        Ø                                                                  
                                                                                        
             0x5800  Shadow PWID LUT 0                                                  
                                                                                 
0x060 0008   0x57FF  Reserved             N/A        N/A      N/A        N/A     N/A
                                                                                        
              Ø        Ø                                                                  
             0x5500  Reserved                                                           
                                                                                 
0x060 0008   0x544F  QWID LUT 15, Bank 4  16         10 Bits  2 Bytes    R/W     7-18
                                                                                        
              Ø        Ø                                                                  
             0x5440                                                                     
                     QWID LUT 0, Bank 4                                                 
                                                                                 
0x060 0008   0x543F  PWID LUT 63, Bank 4  64         10 Bits  2 Bytes    R/W     7-18
                                                                                        
              Ø        Ø                                                                  
             0x5400                                                                     
                     PWID LUT 0, Bank 4                                                 
                                                                                 
0x060 0008   0x534F  QWID LUT 15, Bank 3  16         10 Bits  2 Bytes    R/W     7-18
                                                                                        
              Ø        Ø                                                                  
             0x5340                                                                     
                     QWID LUT 0, Bank 3                                                 
                                                                                 
0x060 0008   0x533F  PWID LUT 63, Bank 3  64         10 Bits  2 Bytes    R/W     7-18
                                                                                        
              Ø        Ø                                                                  
             0x5300                                                                     
                     PWID LUT 0, Bank 3                                                 
                                                                                 
0x060 0008   0x524F  QWID LUT 15, Bank 2  16         10 Bits  2 Bytes    R/W     7-18
                                                                                        
              Ø        Ø                                                                  
             0x5240                                                                     
                     QWID LUT 0, Bank 2                                                 
                                                                                 
0x060 0008   0x523F  PWID LUT 63, Bank 2  64         10 Bits  2 Bytes    R/W     7-18
                                                                                        
              Ø        Ø                                                                  
             0x5200                                                                     
                     PWID LUT 0, Bank 2                                                 
                                                                                 
0x060 0008   0x514F  QWID LUT 15, Bank 1  16         10 Bits  2 Bytes    R/W     7-18
                                                                                        
              Ø        Ø                                                                  
             0x5140                                                                     
                     QWID LUT 0, Bank 1                                                 
                                                                                 
0x060 0008   0x513F  PWID LUT 63, Bank 1  64         10 Bits  2 Bytes    R/W     7-18
                                                                                        
              Ø        Ø                                                                  
             0x5100                                                                     
                     PWID LUT 0, Bank 1                                                 
                                                                                 
0x060 0008   0x504F  QWID LUT 15, Bank 0  16         10 Bits  2 Bytes    R/W     7-18
                                                                                        
              Ø        Ø                                                                  
             0x5040                                                                     
                     QWID LUT 0, Bank 0                                                 
                                                                                 
0x060 0008   0x503F  PWID LUT 63, Bank 0  64         10 Bits  2 Bytes    R/W     7-18
                                                                                        
              Ø        Ø                                                                  
             0x5000                                                                     
                     PWID LUT 0, Bank 0                                                 

---------------------------------------------------------------------------------

Table 4-13 shows the indirectly accessed Fast Clear Buffers and the associated Shadow buffers in the LeoCross Color Tables section of LeoCross. The 16-bit Index value in the table needs to be loaded into the LeoCross Address Pointer to access the register indicated.The Fast Clear Buffers are duplicated twice, called bank 1 and 0, in the hardware for timing reasons. There is no reason to load different values into the two banks in normal operation.

    Table 4-13 LeoCross Color Tables (Indirect) - Fast Clear Buffers

----------------------------------------------------------------------------------------------
SBus Index Register Name Size Device SBus Size Access Page Address Width (# loc's) ----------------------------------------------------------------------------------------------
                                                                                              
0x060 0008   0x41FF     Reserved for other functions   N/A        N/A      N/A        N/A     N/A
                                                                                                     
              Ø           Ø                                                                            
                        Reserved for other functions                                                 
             0x4106                                                                                  
                                                                                              
0x060 0008   0x4105     Shadow Fast Clear Color 5      1          3 Bytes  4 Bytes    R/W     7-15
                                                                                              
0x060 0008   0x4104     Shadow Fast Clear Color 4      1          3 Bytes  4 Bytes    R/W     7-15
                                                                                              
0x060 0008   0x4103     Shadow Fast Clear Color 3      1          3 Bytes  4 Bytes    R/W     7-15
                                                                                              
0x060 0008   0x4102     Shadow Fast Clear Color 2      1          3 Bytes  4 Bytes    R/W     7-15
                                                                                              
0x060 0008   0x4101     Shadow Fast Clear Color 1      1          3 Bytes  4 Bytes    R/W     7-15
                                                                                              
0x060 0008   0x4100     Shadow Fast Clear Color 0      1          3 Bytes  4 Bytes    R/W     7-15
                                                                                              
0x060 0008   0x3FFF     Reserved for other functions   N/A        N/A      N/A        N/A     N/A
                                                                                                     
              Ø           Ø                                                                            
                        Reserved for other functions                                                 
             0x3706                                                                                  
                                                                                              
0x060 0008   0x3705     Fast Clear Color 5, Bank 1     1          3 Bytes  4 Bytes    R/W     7-15
                                                                                              
0x060 0008   0x3704     Fast Clear Color 4, Bank 1     1          3 Bytes  4 Bytes    R/W     7-15
                                                                                              
0x060 0008   0x3703     Fast Clear Color 3, Bank 1     1          3 Bytes  4 Bytes    R/W     7-15
                                                                                              
0x060 0008   0x3702     Fast Clear Color 2, Bank 1     1          3 Bytes  4 Bytes    R/W     7-15
                                                                                              
0x060 0008   0x3701     Fast Clear Color 1, Bank 1     1          3 Bytes  4 Bytes    R/W     7-15
                                                                                              
0x060 0008   0x3700     Fast Clear Color 0, Bank 1     1          3 Bytes  4 Bytes    R/W     7-15
                                                                                              
0x060 0008   0x36FF     Reserved for other functions   N/A        N/A      N/A        N/A     N/A
                                                                                                     
              Ø           Ø                                                                            
                        Reserved for other functions                                                 
             0x3306                                                                                  
                                                                                              
0x060 0008   0x3305     Fast Clear Color 5, Bank 0     1          3 Bytes  4 Bytes    R/W     7-15
                                                                                              
0x060 0008   0x3304     Fast Clear Color 4, Bank 0     1          3 Bytes  4 Bytes    R/W     7-15
                                                                                              
0x060 0008   0x3303     Fast Clear Color 3, Bank 0     1          3 Bytes  4 Bytes    R/W     7-15
                                                                                              
0x060 0008   0x3302     Fast Clear Color 2, Bank 0     1          3 Bytes  4 Bytes    R/W     7-15
                                                                                              
0x060 0008   0x3301     Fast Clear Color 1, Bank 0     1          3 Bytes  4 Bytes    R/W     7-15
                                                                                              
0x060 0008   0x3300     Fast Clear Color 0, Bank 0     1          3 Bytes  4 Bytes    R/W     7-15
                                                                                              
0x060 0008   0x32FF     Reserved for other functions   N/A        N/A      N/A        N/A     N/A
              Ø           Ø                                                                            
                        Reserved for other functions                                                 
             0x3000                                                                                  

----------------------------------------------------------------------------------------------

Table 4-14 shows the indirectly accessed Active Cursor Color LUT's. Note that these tables are accessed via the LeoCross address space rather than the cursor address space. This access is provided for diagnostic purposes only. It is not a path that is used by the cursor circuits or software.

    Table 4-14 LeoCross Color Tables (Indirect) - Active Cursor

----------------------------------------------------------------------------------------------
SBus Index Register Name Size Device SBus Size Access Page Address Width (# loc's) ----------------------------------------------------------------------------------------------
                                                                                              
0x060 0008   0x3FFF   Reserved for other functions   N/A        N/A      N/A        N/A       N/A
              Ø         Ø                                                                              
                      Reserved for other functions                                                   
             0x3708                                                                                  
                                                                                              
0x060 0008   0x3707   Active Cursor Color 1, Bank 1  2          3 Bytes  4 Bytes    Diag R/W  7-16
                                                                                              
0x060 0008   0x3706   Active Cursor Color 0, Bank 1                                           
                                                                                              
0x060 0008   0x3705   Reserved for other functions   N/A        N/A      N/A        N/A       N/A
              Ø         Ø                                                                              
                      Reserved for other functions                                                   
             0x3308                                                                                  
                                                                                              
0x060 0008   0x3307   Active Cursor Color 1, Bank 0  2          3 Bytes  4 Bytes    Diag R/W  7-16
                                                                                              
0x060 0008   0x3306   Active Cursor Color 0, Bank 0                                           
                                                                                              
0x060 0008   0x3305   Reserved for other functions   N/A        N/A      N/A        N/A       N/A
              Ø         Ø                                                                              
                      Reserved for other functions                                                   
             0x3301                                                                                  

----------------------------------------------------------------------------------------------

Table 4-15 shows the indirectly accessed Image Color LUT's and the associated Shadow buffers in the LeoCross Color Tables section of LeoCross. The 16-bit Index value in the table needs to be loaded into the LeoCross Address Pointer to access the register indicated. There are three Color LUT's called CLUT - 2, CLUT - 1, and CLUT - 0. Each Color LUT is duplicated twice, called bank 1 and 0, in the hardware for timing reasons. There is no reason to load different values into the two banks in normal operation. There is a separate Shadow table for each of the three CLUT's.

    Table 4-15 LeoCross Color Tables (Indirect) - Image Color LUTs

----------------------------------------------------------------------------------------------
SBus Index Register Name Size Device SBus Size Access Page Address Width (# loc's) ----------------------------------------------------------------------------------------------
                                                                                              
0x060 0008   0x40FF    Shadow CLUT, Word 255           256        3 Bytes  4 Bytes    R/W     7-15
                                                                                                     
              Ø                                                                                       
             0x4000                                                                                  
                       Shadow CLUT, Word 0                                                           
                                                                                              
0x060 0008   0x3FFF    Reserved for other functions    N/A        N/A      N/A        N/A     N/A
                                                                                                     
              Ø          Ø                                                                             
             0x3700    Reserved for other functions                                                  
                                                                                              
0x060 0008   0x36FF    Image CLUT-2, Word 255, Bank 1  256        3 Bytes  4 Bytes    R/W     7-15
                                                                                                     
              Ø                                                                                       
             0x3600                                                                                  
                       Image CLUT-2, Word 0, Bank 1                                                  
                                                                                              
0x060 0008   0x35FF    Image CLUT-1, Word 255, Bank 1  256        3 Bytes  4 Bytes    R/W     7-15
                                                                                                     
              Ø                                                                                       
             0x3500                                                                                  
                       Image CLUT-1, Word 0, Bank 1                                                  
                                                                                              
0x060 0008   0x34FF    Image CLUT-0, Word 255, Bank 1  256        3 Bytes  4 Bytes    R/W     7-15
                                                                                                     
              Ø                                                                                       
             0x3400                                                                                  
                       Image CLUT-0, Word 0, Bank 1                                                  
                                                                                              
0x060 0008   0x33FF    Reserved for other functions    N/A        N/A      N/A        N/A     N/A
                                                                                                     
              Ø          Ø                                                                             
             0x3300    Reserved for other functions                                                  
                                                                                              
0x060 0008   0x32FF    CLUT 2, Word 255, Bank 0        256        3 Bytes  4 Bytes    R/W     7-15
                                                                                                     
              Ø                                                                                       
             0x3200                                                                                  
                       CLUT 2, Word 0, Bank 0                                                        
                                                                                              
0x060 0008   0x31FF    CLUT 1, Word 255, Bank 0        256        3 Bytes  4 Bytes    R/W     7-15
                                                                                                     
              Ø                                                                                       
             0x3100                                                                                  
                       CLUT 1, Word 0, Bank 0                                                        
                                                                                              
0x060 0008   0x30FF    CLUT 0, Word 255, Bank 0        256        3 Bytes  4 Bytes    R/W     7-15
                                                                                                     
              Ø                                                                                       
             0x3000                                                                                  
                       CLUT 0, Word 0, Bank 0                                                        

----------------------------------------------------------------------------------------------

Table 4-16 shows the indirectly accessed Control Registers in LeoCross. The 16-bit Index value in the table needs to be loaded into the LeoCross Address Pointer to access the register indicated.

    Table 4-16 LeoCross Control Registers (Indirect)

-----------------------------------------------------------------------------------------------
SBus Index Register Name Size Device SBus Size Access Page Address Width (# loc's) -----------------------------------------------------------------------------------------------
                                                                                               
0x060 0004   0x2FFF   Reserved                          N/A        N/A      N/A        N/A     
              Ø         Ø                                                                               
             0x2028   Reserved                                                                        
                                                                                               
0x060 0004   0x2027   Video Clock Generator             1          1 Byte   4 Bytes    R/W     7-51
                                                                                               
0x060 0004   0x2026   Reserved                          1          N/A      N/A        N/A     N/A
                                                                                               
0x060 0004   0x2025   Reserved                          1          N/A      N/A        N/A     N/A
                                                                                               
0x060 0004   0x2024   DRAM Refresh Counter              1          10 Bits  4 Bytes    Read    7-50
                                                                                               
0x060 0004   0x2023   WID Transfer Counter              1          8 Bits   4 Bytes    Read    7-54
                                                                                               
0x060 0004   0x2022   CLUT Transfer Counter             1          8 Bits   4 Bytes    Read    7-55
                                                                                               
0x060 0004   0x2021   Stereo Shutter Switch             1          2 Bytes  4 Bytes    R/W     7-54
                                                                                               
0x060 0004   0x201F   EXmach Image Start Address        1          2 Bytes  4 Bytes    R/W     7-29
                                                                                               
0x060 0004   0x201E   EXmach WID Start Address          1          2 Bytes  4 Bytes    R/W     7-30
                                                                                               
0x060 0004   0x201D   EXmach Loop Count                 1          1 Byte   4 Bytes    R/W     7-30
                                                                                               
0x060 0004   0x201B   Serration Pulse Start Address     1          2 Bytes  4 Bytes    R/W     7-34
                                                                                               
0x060 0004   0x201A   Serration Pulse End Address       1          2 Bytes  4 Bytes    R/W     7-34
                                                                                               
0x060 0004   0x2018   Equalization Interval 2 Start     1          2 Bytes  4 Bytes    R/W     7-33
                      Address                                                                         
                                                                                               
0x060 0004   0x2017   Equalization Interval 2 End       1          2 Bytes  4 Bytes    R/W     7-33
                      Address                                                                         
                                                                                               
0x060 0004   0x2016   Equalization Interval 1 Start     1          2 Bytes  4 Bytes    R/W     7-32
                      Address                                                                         
                                                                                               
0x060 0004   0x2015   Equalization Interval 1 End       1          2 Bytes  4 Bytes    R/W     7-32
                      Address                                                                         
                                                                                               
0x060 0004   0x2014   Equalization Pulse Start Address  1          2 Bytes  4 Bytes    R/W     7-31
                                                                                               
0x060 0004   0x2013   Equalization Pulse End Address    1          2 Bytes  4 Bytes    R/W     7-31
                                                                                               
0x060 0004   0x2012   Vertical Counter (Diagnostic      1          2 Bytes  4 Bytes    Read    7-35
                      Read)                                                                           
                                                                                               
0x060 0004   0x2011   VSynch Start Address              1          2 Bytes  4 Bytes    R/W     7-35
                                                                                               
0x060 0004   0x2010   VSynch End Address                1          2 Bytes  4 Bytes    R/W     7-36
                                                                                               
0x060 0004   0x200F   VBlank Start Address              1          2 Bytes  4 Bytes    R/W     7-36
                                                                                               
0x060 0004   0x200E   VBlank End Address                1          2 Bytes  4 Bytes    R/W     7-37
                                                                                               
0x060 0004   0x200D   Vertical Counter Size             1          2 Bytes  4 Bytes    R/W     7-37
                                                                                               
0x060 0004   0x200C   HSynch Start Address              1          2 Bytes  4 Bytes    R/W     7-39
                                                                                               
0x060 0004   0x200B   HSynch End Address                1          2 Bytes  4 Bytes    R/W     7-39
                                                                                               
0x060 0004   0x200A   Horizontal Counter (Diagnostic    1          2 Bytes  4 Bytes    Read    7-38
                      Read)                                                                           
                                                                                               
0x060 0004   0x2009   HBlank Start Address              1          2 Bytes  4 Bytes    R/W     7-40
                                                                                               
0x060 0004   0x2008   HBlank End Address                1          2 Bytes  4 Bytes    R/W     7-40
                                                                                               
0x060 0004   0x2007   Horizontal Counter Size           1          2 Bytes  4 Bytes    R/W     7-41
                                                                                               
0x060 0004   0x2006   Configuration Register Three      1          1 Byte   4 Bytes    R/W     7-47
                                                                                               
0x060 0004   0x2005   Configuration Register Two        1          1 Byte   4 Bytes    R/W     7-46
                                                                                               
0x060 0004   0x2004   Configuration Register One        1          2 Bytes  4 Bytes    R/W     7-44
                                                                                               
0x060 0004   0x2003   Configuration Register Zero       1          2 Bytes  4 Bytes    R/W     7-42
                                                                                               
0x060 0004   0x2002   DRAM Refresh Count                1          2 Bytes  4 Bytes    R/W     7-50
                                                                                               
0x060 0004   0x2001   Monitor ID                        1          1 Byte   4 Bytes    Read    7-49
                                                                                               
0x060 0004   0x2000   LX Chip Code                      1          4 Bytes  4 Bytes    Read    7-48
                                                                                               
0x060 0004   0x1FFF   Reserved                          N/A        N/A      N/A        N/A     N/A
              Ø         Ø                                                                        
             0x1008   Reserved                                                                 
                                                                                               
0x060 0004   0x1007   Interrupt Clear Mask              1          1 Byte   4 Bytes    Write   7-26
                                                                                               
0x060 0004   0x1006   Interrupt Enable Mask             1          1 Byte   4 Bytes    R/W     7-25
                                                                                               
0x060 0004   0x1005   Interrupt Event                   1          1 Byte   4 Bytes    R/W     7-25
                                                                                               
0x060 0004   0x1003   WID/FC CSR                        1          1 Byte   4 Bytes    R/W     7-22
                                                                                               
0x060 0004   0x1002   Image 2 CSR                       1          1 Byte   4 Bytes    R/W     7-21
                                                                                               
0x060 0004   0x1001   Image 1 CSR                       1          1 Byte   1 Byte     R/W     7-21
                                                                                               
0x060 0004   0x1000   Image 0 CSR                       1          1 Byte   1 Byte     R/W     7-21
                                                                                               
0x060 0004   0x0FFF   Reserved                          N/A        N/A      N/A        N/A     N/A
              Ø         Ø                                                                        
             0x0000   Reserved                                                                 

-----------------------------------------------------------------------------------------------