--- .empty	Thu Jan  1 00:00:00 1970
+++ NEW/xc/programs/Xserver/hw/s24/s24.h	Thu Jan  1 00:00:00 1970
@@ -0,0 +1,123 @@
+#ifndef _S24_H_b5324fe2_
+#define _S24_H_b5324fe2_
+
+#include <sys/time.h>
+
+struct s24dac {
+  unsigned int addr;
+  unsigned int clut;
+  unsigned int ctl1;
+  unsigned int olut;
+  unsigned int addr2; /* duplicate of addr */
+  unsigned int clut2; /* duplicate of clut */
+  unsigned int ctl2;
+  unsigned int olut2; /* duplicate of olut */
+  } ;
+
+/* addresses for indirect access through ctl1 */
+/* 2 and 3: documented as reserved.  8 and up: not documented at all. */
+#define S24_DAC_CTL1_ID         0x00
+#define S24_DAC_CTL1_REV        0x01
+#define S24_DAC_CTL1_READ_MASK  0x04 /* ANDed with pixel values */
+#define S24_DAC_CTL1_BLINK_MASK 0x05 /* Blink-ANDed with pixel valeus */
+#define S24_DAC_CTL1_CTL_0      0x06
+/* Does overlay bits 00 display overlay colour 0 or pixel data? */
+#define S24_DAC_CTL1_CTL0_OVL_PIX 0x40
+#define S24_DAC_CTL1_CTL0_OVL_PIX_OVL 0x00 /* overlay colour 0 */
+#define S24_DAC_CTL1_CTL0_OVL_PIX_PIX 0x40 /* pixel data */
+/* What rate do blinking things blink at? */
+#define S24_DAC_CTL1_CTL0_BLINKRATE 0x30
+/* _BLINK_xx_yy = xx frames on, yy frames off */
+#define S24_DAC_CTL1_CTL0_BLINK_16_48 0x00
+#define S24_DAC_CTL1_CTL0_BLINK_16_16 0x10
+#define S24_DAC_CTL1_CTL0_BLINK_32_32 0x20
+#define S24_DAC_CTL1_CTL0_BLINK_64_64 0x30
+#define S24_DAC_CTL1_CTL0_OVL_BLINK 0xc0
+#define S24_DAC_CTL1_CTL0_OVL_BLINK_NONE 0x00
+#define S24_DAC_CTL1_CTL0_OVL_BLINK_EVEN 0x40
+#define S24_DAC_CTL1_CTL0_OVL_BLINK_ODD  0x80
+#define S24_DAC_CTL1_CTL0_OVL_BLINK_BOTH 0xc0
+#define S24_DAC_CTL1_CTL0_OVL_ENABLE 0x03
+#define S24_DAC_CTL1_CTL0_OVL_ENABLE_NONE 0x00
+#define S24_DAC_CTL1_CTL0_OVL_ENABLE_EVEN 0x01
+#define S24_DAC_CTL1_CTL0_OVL_ENABLE_ODD  0x02
+#define S24_DAC_CTL1_CTL0_OVL_ENABLE_BOTH 0x03
+#define S24_DAC_CTL1_TEST_0     0x07 /* details not documented here */
+
+/* addresses for indirect access through ctl2 */
+/* a and f: documented as reserved; 12 and up: not documented at all */
+#define S24_DAC_CTL2_CTL1 0x08 /* no useful bits */
+#define S24_DAC_CTL2_CTL2 0x09
+/* 0xb0 bits docuemnted as reserved */
+#define S24_DAC_CTL2_CTL2_PEDESTAL 0x40
+#define S24_DAC_CTL2_CTL2_SYOUT_SRC 0x0a
+/* values 0x02 and 0x0a have the same semantics as _SYNC. */
+#define S24_DAC_CTL2_CTL2_SYOUT_SRC_SYNC  0x00 /* use SYNC */
+#define S24_DAC_CTL2_CTL2_SYOUT_SRC_BLANK 0x08 /* use BLANK */
+#define S24_DAC_CTL2_CTL2_SYOUT_ENABLE 0x04
+#define S24_DAC_CTL2_CTL2_TEST_TYPE 0x01
+#define S24_DAC_CTL2_CTL2_TEST_TYPE_SIG  0x00
+#define S24_DAC_CTL2_CTL2_TEST_TYPE_DATA 0x01
+#define S24_DAC_CTL2_TEST1 0x0b
+/* 0xf7 bits documented as reserved */
+#define S24_DAC_CTL2_TEST1_OCMP 0x08
+#define S24_DAC_CTL2_TEST1_OCMP_HIGH 0x00
+#define S24_DAC_CTL2_TEST1_OCMP_LOW  0x08
+#define S24_DAC_CTL2_RSAR 0x0c
+#define S24_DAC_CTL2_GSAR 0x0d
+#define S24_DAC_CTL2_BSAR 0x0e
+#define S24_DAC_CTL2_CTL3 0x10
+/* 0x40 bit documented as reserved */
+#define S24_DAC_CTL2_CTL3_MODE 0x80
+#define S24_DAC_CTL2_CTL3_MODE_467 /* dumb */
+#define S24_DAC_CTL2_CTL3_MODE_567 /* smart */
+#define S24_DAC_CTL2_CTL3_PXIT 0x20 /* pixel interface timing */
+#define S24_DAC_CTL2_CTL3_PXIT_467 0x00
+#define S24_DAC_CTL2_CTL3_PXIT_567 0x20
+#define S24_DAC_CTL2_CTL3_SLEEP 0x10
+#define S24_DAC_CTL2_CTL3_SLEEP_AWAKE  0x00
+#define S24_DAC_CTL2_CTL3_SLEEP_ASLEEP 0x10
+#define S24_DAC_CTL2_CTL3_BYPASS 0x0f
+#define S24_DAC_CTL2_CTL3_BYPASS_NORM 0x00
+#define S24_DAC_CTL2_CTL3_BYPASS_PSEUDO 0x0a
+#define S24_DAC_CTL2_CTL3_BYPASS_DIRECT 0x08
+#define S24_DAC_CTL2_CTL3_BYPASS_TRUE   0x0c
+#define S24_DAC_CTL2_CTL3_BYPASS_TGAMMA 0x09
+#define S24_DAC_CTL2_CTL4 0x11
+/* 0x0c bits documented as reserved */
+#define S24_DAC_CTL2_CTL4_PLLENB 0x80 /* don't meddle */
+#define S24_DAC_CTL2_CTL4_TEST   0x40 /* enable output on test pins */
+#define S24_DAC_CTL2_CTL4_BPP    0x30
+/* I have no idea what controls whether mode 0x10 is 5/5/5 or 4/4/4+ctl */
+#define S24_DAC_CTL2_CTL4_BPP_8PSEUDO 0x00 /* 8bpp */
+#define S24_DAC_CTL2_CTL4_BPP_555 0x10     /* 16bpp, 5/5/5, or 4/4/4+ctl */
+#define S24_DAC_CTL2_CTL4_BPP_565 0x20     /* 16bpp, 5/6/5 */
+#define S24_DAC_CTL2_CTL4_BPP_888 0x30     /* 32bpp, 8/8/8+ctl */
+#define S24_DAC_CTL2_CTL4_PIXPINS 0x03
+/* value 0x03 documented as reserved */
+#define S24_DAC_CTL2_CTL4_PIXPINS_16 0x00
+#define S24_DAC_CTL2_CTL4_PIXPINS_32 0x01
+#define S24_DAC_CTL2_CTL4_PIXPINS_64 0x02
+
+struct s24tec {
+  char pad1[0x8fc];
+  unsigned int cursloc;
+#define S24_CURSLOC(x,y) ((0x10000*(unsigned int)(x))|(0xffff&(unsigned int)(y)))
+  unsigned int curs_a[32];
+  unsigned int curs_b[32];
+  } ;
+
+extern volatile struct s24dac *s24_dac;
+extern volatile struct s24tec *s24_tec;
+extern void *s24_dfb8;
+extern void *s24_dfb24;
+extern void *s24_rdfb32;
+extern void *s24_blit;
+extern void *s24_stip;
+extern void *s24_rblit;
+extern void *s24_rstip;
+
+extern void s24_block_handler(int, void *, struct timeval **, void *);
+extern void s24_wakeup_handler(int, void *, unsigned long int, void *);
+
+#endif