The assembly code in reald-s.s is designed to execute a semi-arbitrary
instruction with controlled context, returning after updating the
context.

It works by setting the instruction into a small snippet of data
segment (with suitable FLUSHes and STBARs).  It then sets up everything
and reaches the instruction via a ret/restore pair.  After the
instruction, we do a save, sethi, or, and call to get back into the
text segment with a useful value in a register.  We then flush things
back to the state struct and return.

On entry, %o0 points to 34 32-bit ints.  The first is the instruction
to execute.  The next 32 are register contents.  The last has condition
codes in its low 4 bits; the high 28 bits are ignored on input and
meaningless on output.

This does not work for instructions that mess with %sp, shift register
windows (eg, save or restore), or that affect control flow.

The input register values corresponding to %sp and %fp are ignored.

The code uses three register windows.

We are entered in our caller's window (C).  Input is in %o0, return PC
in %o7.  We save three times.  The first one is to make it easy to
preserve the return PC value.  The second one gets us in the window
we'll execute the subject instruction in.  The third one gets us into a
scratch window we can set up the last pieces in.  We then jmpl/restore,
execute the instruction, save/sethi/or/call, and we're back in our
scratch window.

%g0-%g7 are registers 0-7
%o0-%o7 are registers 8-15 (%o6 is %sp)
%l0-%l7 are register 16-23
%i0-%i7 are registers 24-31 (%i6 is %fp)

addcc:

N = result<31>
Z = result==0
V = (src1<31> & src2<31> & !dst<31>) | (!src1<31> & !src2<31> & dst<31>)
C = (src1<31> & src2<31>) | (!dst<31> & (src1<31> | src2<31>))

taddcc:

like addcc, except V is |ed with (src1<1:0> != 0) | (src2<1:0> != 0).

subcc:

N = result<31>
Z = result==0
V = (src1<31> & !src2<31> & !dst<31>) | (!src1<31> & src2<31> & dst<31>)
C = (!src1<31> & src2<31>) | (dst<31> & (!src1<31> | src2<31>))

tsubcc:

tsubcc : subcc :: taddcc : addcc

mulscc:

N = result<31>
Z = result==0
V = (src1<31> & src2<31> & !dst<31>) | (!src1<31> & !src2<31> & dst<31>)
C = (src1<31> & src2<31>) | (!dst<31> & (src1<31> | src2<31>))

umulcc, smulcc:

N = result<31>
Z = result==0
V = 0
C = 0

udivcc, sdivcc:

N = result<31>
Z = result==0
V = 32-bit overflow
C = 0