.list push off ; Here's what the 8139c PDF, run through pdftotext, says. This PDF is ; the one from http://realtek.info/pdf/rtl8139c.pdf; Realtek's own doc ; is, as far as I can tell from my minimal Web skillz on their ; webpages, NDAed. Perhaps they're too ashamed of their design to ; admit to the world how crappy it is? ; Section 6, Register Descriptions. ; "The RTL8139C(L) provides the following set of operational registers ; mapped into PCI memory space or I/O space." ; I've reformatted this text a bit. ; 0000 R/W IDR0 ID Register 0: The ID registers 0-5 are ; only permitted to read/write by 4-byte ; access. Read access can be byte, word, ; or double word access. The initial ; value is autoloaded from the EEPROM ; EthernetID field. ; 0001 R/W IDR1 ID Register 1 ; 0002 R/W IDR2 ID Register 2 ; 0003 R/W IDR3 ID Register 3 ; 0004 R/W IDR4 ID Register 4 ; 0005 R/W IDR5 ID Register 5 ; 0006-0007 - - Reserved ; 0008 R/W MAR0 Multicast Register 0: The MAR registers ; 0-7 are only permitted to read/write by ; 4-byte access. Read access can be ; byte, word, or double word access. ; Driver is responsible for initializing ; these registers. ; 0009 R/W MAR1 Multicast Register 1 ; 000A R/W MAR2 Multicast Register 2 ; 000B R/W MAR3 Multicast Register 3 ; 000C R/W MAR4 Multicast Register 4 ; 000D R/W MAR5 Multicast Register 5 ; 000E R/W MAR6 Multicast Register 6 ; 000F R/W MAR7 Multicast Register 7 ; 0010-0013 R/W TSD0 Transmit Status of Descriptor 0 ; 0014-0017 R/W TSD1 Transmit Status of Descriptor 1 ; 0018-001B R/W TSD2 Transmit Status of Descriptor 2 ; 001C-001F R/W TSD3 Transmit Status of Descriptor 3 ; 0020-0023 R/W TSAD0 Transmit Start Address of Descriptor0 ; 0024-0027 R/W TSAD1 Transmit Start Address of Descriptor1 ; 0028-002B R/W TSAD2 Transmit Start Address of Descriptor2 ; 002C-002F R/W TSAD3 Transmit Start Address of Descriptor3 ; 0030-0033 R/W RBSTART Receive (Rx) Buffer Start Address ; 0034-0035 R ERBCR Early Receive (Rx) Byte Count Register ; 0036 R ERSR Early Rx Status Register ; 0037 R/W CR Command Register ; 0038-0039 R/W CAPR Current Address of Packet Read (initial ; value is 0FFF0) ; 003A-003B R CBR Current Buffer Address: The initial ; value is 0000. It reflects total ; received byte-count in the rx buffer. ; 003C-003D R/W IMR Interrupt Mask Register ; 003E-003F R/W ISR Interrupt Status Register ; 0040-0043 R/W TCR Transmit (Tx) Configuration Register ; 0044-0047 R/W RCR Receive (Rx) Configuration Register ; 0048-004B R/W TCTR Timer Count Register: This register ; contains a 32-bit general-purpose ; timer. Writing any value to this ; 32-bit register will reset the original ; timer and begin to count from zero. ; 004C-004F R/W MPC Missed Packet Counter: Indicates the ; number of packets discarded due to rx ; FIFO overflow. It is a 24-bit counter. ; After s/w reset, MPC is cleared. Only ; the lower 3 bytes are valid. When any ; value is written, MPC will be reset ; also. ; 0050 R/W 9346CR 93C46 (93C56) Command Register ; 0051 R/W CONFIG0 Configuration Register 0 ; 0052 R/W CONFIG1 Configuration Register 1 ; 0053 - - Reserved ; 0054-0057 R/W TimerInt Timer Interrupt Register: Once having ; written a nonzero value to this ; register, the Timeout bit of ISR ; register will be set whenever the TCTR ; reaches to this value. The Timeout bit ; will never be set as long as TimerInt ; register is zero. ; 0058 R/W MSR Media Status Register ; 0059 R/W CONFIG3 Configuration register 3 ; 005A R/W CONFIG4 Configuration register 4 ; 005B - - Reserved ; 005C-005D R/W MULINT Multiple Interrupt Select ; 005E R RERID PCI Revision ID = 10h ; 005F - - Reserved ; 0060-0061 R TSAD Transmit Status of All Descriptors ; 0062-0063 R/W BMCR Basic Mode Control Register ; 0064-0065 R BMSR Basic Mode Status Register ; 0066-0067 R/W ANAR Auto-Negotiation Advertisement Register ; 0068-0069 R ANLPAR Auto-Negotiation Link Partner Register ; 006A-006B R ANER Auto-Negotiation Expansion Register ; 006C-006D R DIS Disconnect Counter ; 006E-006F R FCSC False Carrier Sense Counter ; 0070-0071 R/W NWAYTR N-way Test Register ; 0072-0073 R REC RX_ER Counter ; 0074-0075 R/W CSCR CS Configuration Register ; 0076-0077 - - Reserved ; 0078-007B R/W PHY1_PARM PHY parameter 1 ; 007C-007F R/W TW_PARM Twister parameter ; 0080 R/W PHY2_PARM PHY parameter 2 ; 0081-0083 - - Reserved ; 0084 R/W CRC0 Power Management CRC Register0 for Wakeup Frame0 ; 0085 R/W CRC1 Power Management CRC Register1 for Wakeup Frame1 ; 0086 R/W CRC2 Power Management CRC Register2 for Wakeup Frame2 ; 0087 R/W CRC3 Power Management CRC Register3 for Wakeup Frame3 ; 0088 R/W CRC4 Power Management CRC Register4 for Wakeup Frame4 ; 0089 R/W CRC5 Power Management CRC Register5 for Wakeup Frame5 ; 008A R/W CRC6 Power Management CRC Register6 for Wakeup Frame6 ; 008B R/W CRC7 Power Management CRC Register7 for Wakeup Frame7 ; 008C­0093 R/W Wakeup0 Power Management Wakeup Frame0 (64bit) ; 0094­009B R/W Wakeup1 Power Management Wakeup Frame1 (64bit) ; 009C­00A3 R/W Wakeup2 Power Management Wakeup Frame2 (64bit) ; 00A4­00AB R/W Wakeup3 Power Management Wakeup Frame3 (64bit) ; 00AC­00B3 R/W Wakeup4 Power Management Wakeup Frame4 (64bit) ; 00B4­00BB R/W Wakeup5 Power Management Wakeup Frame5 (64bit) ; 00BC­00C3 R/W Wakeup6 Power Management Wakeup Frame6 (64bit) ; 00C4­00CB R/W Wakeup7 Power Management Wakeup Frame7 (64bit) ; 00CC R/W LSBCRC0 LSB of the Mask byte of Wakeup Frame0 Within Offset 12 to 75 ; 00CD R/W LSBCRC1 LSB of the Mask byte of Wakeup Frame1 Within Offset 12 to 75 ; 00CE R/W LSBCRC2 LSB of the Mask byte of Wakeup Frame2 Within Offset 12 to 75 ; 00CF R/W LSBCRC3 LSB of the Mask byte of Wakeup Frame3 Within Offset 12 to 75 ; 00D0 R/W LSBCRC4 LSB of the Mask byte of Wakeup Frame4 Within Offset 12 to 75 ; 00D1 R/W LSBCRC5 LSB of the Mask byte of Wakeup Frame5 Within Offset 12 to 75 ; 00D2 R/W LSBCRC6 LSB of the Mask byte of Wakeup Frame6 Within Offset 12 to 75 ; 00D3 R/W LSBCRC7 LSB of the Mask byte of Wakeup Frame7 Within Offset 12 to 75 ; 00D4-00D7 R/W FLASH Flash Memory Read/Write Register ; 00D8 R/W Config5 Configuration Register 5 ; 00D9-00EF - - Reserved ; 00F0-00F3 R/W FER Function Event Register (Cardbus only) ; 00F4-00F7 R/W FEMR Function Event Mask Register (CardBus only) ; 00F8-00FB R FPSR Function Present State Register (CardBus only) ; 00FC-00FF W FFER Function Force Event Register (CardBus only) BBA_RTK_MAC = 0x00 ; first of 6 BBA_RTK_MULTI_FILTER = 0x08 ; first of 8 BBA_RTK_TXSTAT = 0x10 ; first of 4 BBA_RTK_TXSTAT_LOST_CARRIER = 0x80000000 BBA_RTK_TXSTAT_ABORTED = 0x40000000 BBA_RTK_TXSTAT_LATE_COLL = 0x20000000 BBA_RTK_TXSTAT_HEARTBEAT = 0x10000000 BBA_RTK_TXSTAT_NCOLL_SHIFT = 24 BBA_RTK_TXSTAT_NCOLL_BITS = 4 BBA_RTK_TXSTAT_NCOLL_MASK = 0xf ; 0x00c00000 reserved BBA_RTK_TXSTAT_EARLYTXTHRESH_SHIFT = 16 BBA_RTK_TXSTAT_EARLYTXTHRESH_BITS = 6 BBA_RTK_TXSTAT_EARLYTXTHRESH_MASK = 0x3f BBA_RTK_TXSTAT_TXOK = 0x00008000 BBA_RTK_TXSTAT_UNDERRUN = 0x00004000 BBA_RTK_TXSTAT_OWN = 0x00002000 BBA_RTK_TXSTAT_SIZE_SHIFT = 0 BBA_RTK_TXSTAT_SIZE_BITS = 13 BBA_RTK_TXSTAT_SIZE_MASK = 0x1fff BBA_RTK_TXADDR = 0x20 ; first of 4 BBA_RTK_RXSTART = 0x30 BBA_RTK_EARLY_RX_COUNT = 0x34 BBA_RTK_EARLY_RX_STAT = 0x36 ; 0xf0 reserved BBA_RTK_EARLY_RX_STAT_GOOD = 0x08 BBA_RTK_EARLY_RX_STAT_BAD = 0x04 BBA_RTK_EARLY_RX_STAT_OVERWRITE = 0x02 BBA_RTK_EARLY_RX_STAT_OK = 0x01 BBA_RTK_COMMAND = 0x37 ; 0xe0 reserved BBA_RTK_COMMAND_RESET = 0x10 BBA_RTK_COMMAND_ENABLE_RX = 0x08 BBA_RTK_COMMAND_ENABLE_TX = 0x04 BBA_RTK_COMMAND_RXBUF_EMPTY = 0x01 BBA_RTK_CUR_PKT_READ = 0x38 BBA_RTK_CUR_RX_PTR = 0x3a BBA_RTK_INTR_MASK = 0x3c BBA_RTK_INTR_STAT = 0x3e ; These bits apply to both INTR_MASK and INTR_STAT BBA_RTK_INTR_SYSERR = 0x8000 BBA_RTK_INTR_TIMEOUT = 0x4000 BBA_RTK_INTR_LENCHG = 0x2000 ; 0x1fc0 reserved BBA_RTK_INTR_RXFOVF = 0x0040 BBA_RTK_INTR_UND_LINK = 0x0020 BBA_RTK_INTR_RXBOVF = 0x0010 BBA_RTK_INTR_TXERR = 0x0008 BBA_RTK_INTR_TXOK = 0x0004 BBA_RTK_INTR_RXERR = 0x0002 BBA_RTK_INTR_RXOK = 0x0001 BBA_RTK_TXCFG = 0x40 ; 0x80000000 reserved BBA_RTK_TXCFG_HWREV_SHIFT = 26 BBA_RTK_TXCFG_HWREV_BITS = 4 BBA_RTK_TXCFG_HWREV_MASK = 0xf BBA_RTK_TXCFG_IFG_SHIFT = 24 BBA_RTK_TXCFG_IFG_BITS = 2 BBA_RTK_TXCFG_IFG_MASK = 3 BBA_RTK_TXCFG_8139A_G = 0x00100000 ; 0x00780000 reserved BBA_RTK_TXCFG_LOOPBACK = 0x00060000 BBA_RTK_TXCFG_LOOPBACK_NORMAL = 0x00000000 ; 0x00020000 and 0x00040000 reserved BBA_RTK_TXCFG_LOOPBACK_LOOP = 0x00060000 BBA_RTK_TXCFG_SUPPRESS_CRC = 0x00010000 ; 0x0000f800 BBA_RTK_TXCFG_MAXDMA_SHIFT = 8 BBA_RTK_TXCFG_MAXDMA_BITS = 3 BBA_RTK_TXCFG_MAXDMA_MASK = 7 BBA_RTK_TXCFG_MAXDMA_16 = 0 BBA_RTK_TXCFG_MAXDMA_32 = 1 BBA_RTK_TXCFG_MAXDMA_64 = 2 BBA_RTK_TXCFG_MAXDMA_128 = 3 BBA_RTK_TXCFG_MAXDMA_256 = 4 BBA_RTK_TXCFG_MAXDMA_512 = 5 BBA_RTK_TXCFG_MAXDMA_1024 = 6 BBA_RTK_TXCFG_MAXDMA_2048 = 7 BBA_RTK_TXCFG_RETRIES_SHIFT = 4 ; retry count = 16 * (value + 1) BBA_RTK_TXCFG_RETRIES_BITS = 4 BBA_RTK_TXCFG_RETRIES_MASK = 0xf ; 0x0000000e reserved BBA_RTK_TXCFG_CLRABRT = 0x00000001 BBA_RTK_RXCFG = 0x44 ; 0xf0000000 reserved BBA_RTK_RXCFG_EARLYTHRESH_SHIFT = 24 ; value is sixteenths of packet BBA_RTK_RXCFG_EARLYTHRESH_BITS = 4 BBA_RTK_RXCFG_EARLYTHRESH_MASK = 0xf ; 0x00fc0000 reserved BBA_RTK_RXCFG_MULTEARLYINT = 0x00020000 BBA_RTK_RXCFG_ERROR_8 = 0x00010000 BBA_RTK_RXCFG_FIFOTHRESH_SHIFT = 13 BBA_RTK_RXCFG_FIFOTHRESH_BITS = 3 BBA_RTK_RXCFG_FIFOTHRESH_MASK = 7 BBA_RTK_RXCFG_FIFOTHRESH_16 = 0 BBA_RTK_RXCFG_FIFOTHRESH_32 = 1 BBA_RTK_RXCFG_FIFOTHRESH_64 = 2 BBA_RTK_RXCFG_FIFOTHRESH_128 = 3 BBA_RTK_RXCFG_FIFOTHRESH_256 = 4 BBA_RTK_RXCFG_FIFOTHRESH_512 = 5 BBA_RTK_RXCFG_FIFOTHRESH_1024 = 6 BBA_RTK_RXCFG_FIFOTHRESH_INF = 7 BBA_RTK_RXCFG_BUFSIZ_SHIFT = 11 BBA_RTK_RXCFG_BUFSIZ_BITS = 2 BBA_RTK_RXCFG_BUFSIZ_MASK = 3 BBA_RTK_RXCFG_BUFSIZ_8208 = 0 BBA_RTK_RXCFG_BUFSIZ_16400 = 1 BBA_RTK_RXCFG_BUFSIZ_32784 = 2 BBA_RTK_RXCFG_BUFSIZ_65552 = 3 BBA_RTK_RXCFG_DMABURST_SHIFT = 8 BBA_RTK_RXCFG_DMABURST_BITS = 3 BBA_RTK_RXCFG_DMABURST_MASK = 7 BBA_RTK_RXCFG_DMABURST_16 = 0 BBA_RTK_RXCFG_DMABURST_32 = 1 BBA_RTK_RXCFG_DMABURST_64 = 2 BBA_RTK_RXCFG_DMABURST_128 = 3 BBA_RTK_RXCFG_DMABURST_256 = 4 BBA_RTK_RXCFG_DMABURST_512 = 5 BBA_RTK_RXCFG_DMABURST_1024 = 6 BBA_RTK_RXCFG_DMABURST_INF = 7 BBA_RTK_RXCFG_WRAP = 0x00000080 BBA_RTK_RXCFG_EETYPE = 0x00000040 BBA_RTK_RXCFG_ACCEPT_ERR = 0x00000020 BBA_RTK_RXCFG_ACCEPT_RUNT = 0x00000010 BBA_RTK_RXCFG_ALL_BCAST = 0x00000008 BBA_RTK_RXCFG_ALL_MCAST = 0x00000004 BBA_RTK_RXCFG_MY_UCAST = 0x00000002 BBA_RTK_RXCFG_ALL_UCAST = 0x00000001 BBA_RTK_TIMER_COUNT = 0x48 BBA_RTK_MISS_COUNT = 0x4c BBA_RTK_EECMD = 0x50 BBA_RTK_EECMD_MODE_SHIFT = 6 BBA_RTK_EECMD_MODE_BITS = 2 BBA_RTK_EECMD_MODE_MASK = 3 BBA_RTK_EECMD_MODE_NORMAL = 0 BBA_RTK_EECMD_MODE_AUTOLOAD = 1 BBA_RTK_EECMD_MODE_PROGRAM = 2 BBA_RTK_EECMD_MODE_CONFIG = 3 ; 0x30 reserved BBA_RTK_EECMD_PROGRAM_EECS = 0x08 BBA_RTK_EECMD_PROGRAM_EESK = 0x04 BBA_RTK_EECMD_PROGRAM_EEDI = 0x02 BBA_RTK_EECMD_PROGRAM_EEDO = 0x01 BBA_RTK_CFG0 = 0x51 BBA_RTK_CFG0_SCRAMBLER = 0x80 BBA_RTK_CFG0_PCS = 0x40 BBA_RTK_CFG0_10MB = 0x20 BBA_RTK_CFG0_10TYPE_SHIFT = 3 BBA_RTK_CFG0_10TYPE_BITS = 2 BBA_RTK_CFG0_10TYPE_MASK = 3 BBA_RTK_CFG0_10TYPE_VALUE = 2 BBA_RTK_CFG0_ROMSIZE_SHIFT = 0 BBA_RTK_CFG0_ROMSIZE_BITS = 3 BBA_RTK_CFG0_ROMSIZE_MASK = 7 BBA_RTK_CFG0_ROMSIZE_NONE = 0 BBA_RTK_CFG0_ROMSIZE_8K = 1 BBA_RTK_CFG0_ROMSIZE_16K = 2 BBA_RTK_CFG0_ROMSIZE_32K = 3 BBA_RTK_CFG0_ROMSIZE_64K = 4 BBA_RTK_CFG0_ROMSIZE_128K = 5 ; 6, 7 unused BBA_RTK_CFG1 = 0x52 BBA_RTK_CFG1_LED1 = 0x80 BBA_RTK_CFG1_LED0 = 0x40 BBA_RTK_CFG1_DRIVERLOAD = 0x20 BBA_RTK_CFG1_WAKE_LEVEL = 0x10 BBA_RTK_CFG1_WAKE_LEVEL_H = 0x00 BBA_RTK_CFG1_WAKE_LEVEL_L = 0x10 BBA_RTK_CFG1_MEMMAP = 0x08 BBA_RTK_CFG1_IOMAP = 0x04 BBA_RTK_CFG1_VPD = 0x02 BBA_RTK_CFG1_PME = 0x01 BBA_RTK_TIMER_INT = 0x54 BBA_RTK_MEDIA_STATUS = 0x58 BBA_RTK_MEDIA_STATUS_TXFLOW = 0x80 BBA_RTK_MEDIA_STATUS_RXFLOW = 0x40 ; 0x20 reserved BBA_RTK_MEDIA_STATUS_AUXPWR = 0x10 BBA_RTK_MEDIA_STATUS_10MB = 0x08 BBA_RTK_MEDIA_STATUS_NOLINK = 0x04 BBA_RTK_MEDIA_STATUS_TXPAUSE = 0x02 BBA_RTK_MEDIA_STATUS_RXPAUSE = 0x01 BBA_RTK_CFG3 = 0x59 BBA_RTK_CFG3_GRANTSEL = 0x80 BBA_RTK_CFG3_PARM_ENB = 0x40 BBA_RTK_CFG3_MAGICPKT = 0x20 BBA_RTK_CFG3_WAKELINK = 0x10 BBA_RTK_CFG3_CARDBUS = 0x08 BBA_RTK_CFG3_CLKRUN = 0x04 BBA_RTK_CFG3_CB_FXN = 0x02 BBA_RTK_CFG3_FASTBACK = 0x01 BBA_RTK_CFG4 = 0x5a BBA_RTK_CFG4_RXFOCLR = 0x80 BBA_RTK_CFG4_ANALOG_PWROFF = 0x40 BBA_RTK_CFG4_LONGWAKE = 0x20 BBA_RTK_CFG4_LWAKE_VS_PMEB = 0x10 ; 0x08 reserved BBA_RTK_CFG4_LWAKE_KIND = 0x04 BBA_RTK_CFG4_LWAKE_KIND_LEVEL = 0x00 BBA_RTK_CFG4_LWAKE_KIND_PULSE = 0x04 ; 0x02 reserved BBA_RTK_CFG4_PREBOOT_WAKE = 0x01 BBA_RTK_MULTI_INTR = 0x5c ; 0xf000 reserved BBA_RTK_MULTI_INTR_SHIFT = 0 BBA_RTK_MULTI_INTR_BITS = 12 BBA_RTK_MULTI_INTR_MASK = 0xfff BBA_RTK_PCI_REV_ID = 0x5e BBA_RTK_PCI_REV_ID_VALUE = 0x10 BBA_RTK_TX_STATUS_ALL = 0x60 ; All these need to be shifted by the descriptor number. ; Shift left by 0, 1, 2, or 3 bits for descriptor 0, 1, 2, or 3. BBA_RTK_TX_STATUS_TOK = 0x1000 BBA_RTK_TX_STATUS_TUN = 0x0100 BBA_RTK_TX_STATUS_TABT = 0x0010 BBA_RTK_TX_STATUS_OWN = 0x0001 BBA_RTK_BASIC_MODE_CTL = 0x62 BBA_RTK_BASIC_MODE_CTL_RESET = 0x8000 ; 0x4000 reserved BBA_RTK_BASIC_MODE_CTL_SPEED = 0x2000 BBA_RTK_BASIC_MODE_CTL_SPEED_10MB = 0x0000 BBA_RTK_BASIC_MODE_CTL_SPEED_100MB = 0x2000 BBA_RTK_BASIC_MODE_CTL_NWAY_ENB = 0x1000 ; 0x0c00 reserved BBA_RTK_BASIC_MODE_CTL_RESET_NWAY = 0x0200 BBA_RTK_BASIC_MODE_CTL_DUPLEX = 0x0100 BBA_RTK_BASIC_MODE_CTL_DUPLEX_HALF = 0x0000 BBA_RTK_BASIC_MODE_CTL_DUPLEX_FULL = 0x0100 ; 0x00ff reserved BBA_RTK_BASIC_MODE_STAT = 0x64 BBA_RTK_BASIC_MODE_STAT_100BT4_ENB = 0x8000 BBA_RTK_BASIC_MODE_STAT_100BTX_FD_ENB = 0x4000 BBA_RTK_BASIC_MODE_STAT_100BTX_HD_ENB = 0x2000 BBA_RTK_BASIC_MODE_STAT_10BT_FD_ENB = 0x1000 BBA_RTK_BASIC_MODE_STAT_10BT_HD_ENB = 0x0800 ; 0x07c0 reserved BBA_RTK_BASIC_MODE_STAT_AUTO_DONE = 0x0020 BBA_RTK_BASIC_MODE_STAT_REMFAULT = 0x0010 BBA_RTK_BASIC_MODE_STAT_AUTO_NOFAIL = 0x0008 BBA_RTK_BASIC_MODE_STAT_LINK_UP = 0x0004 BBA_RTK_BASIC_MODE_STAT_JABBER = 0x0002 BBA_RTK_BASIC_MODE_STAT_EXTENDED = 0x0001 BBA_RTK_AUTONEG_ADV = 0x66 BBA_RTK_AUTONEG_PARTNER = 0x68 ; These bits apply to both AUTONEG_ADV and AUTONEG_PARTNER. BBA_RTK_AUTONEG_PAGE = 0x8000 BBA_RTK_AUTONEG_PAGE_PRIMARY = 0x0000 BBA_RTK_AUTONEG_PAGE_SPECIFIC = 0x8000 BBA_RTK_AUTONEG_ACK_CAPS = 0x4000 BBA_RTK_AUTONEG_REMFAULT = 0x2000 ; 0x1800 reserved BBA_RTK_AUTONEG_FLOW_SUPP = 0x0400 BBA_RTK_AUTONEG_100BT4_SUPP = 0x0200 BBA_RTK_AUTONEG_100BTX_FD_SUPP = 0x0100 BBA_RTK_AUTONEG_100BTX_SUPP = 0x0080 BBA_RTK_AUTONEG_10BT_FD_SUPP = 0x0040 BBA_RTK_AUTONEG_10BT_SUPP = 0x0020 BBA_RTK_AUTONEG_PROTO_SHIFT = 0 BBA_RTK_AUTONEG_PROTO_BITS = 5 BBA_RTK_AUTONEG_PROTO_MASK = 0x1f BBA_RTK_AUTONEG_PROTO_CSMA_CD = 1 ; other values not specified/supported BBA_RTK_AUTONEG_EXP = 0x6a ; 0xffe0 reserved BBA_RTK_AUTONEG_EXP_MULT_FAULT = 0x0010 BBA_RTK_AUTONEG_EXP_PEER_NXTP_SUPP = 0x0008 BBA_RTK_AUTONEG_EXP_LOCAL_NXTP_SUPP = 0x0004 BBA_RTK_AUTONEG_EXP_NEWPAGE_RX = 0x0002 BBA_RTK_AUTONEG_EXP_PEER_NWAY_SUPP = 0x0001 BBA_RTK_DISCONNECTS = 0x6c BBA_RTK_FALSE_CARRIER = 0x6e BBA_RTK_NWAY_TEST = 0x70 ; 0xff00 reserved BBA_RTK_NWAY_TEST_LOOPBACK = 0x0080 ; 0x0070 reserved BBA_RTK_NWAY_TEST_LED0_LINK = 0x0008 BBA_RTK_NWAY_TEST_AUTO_ABILITY_DET = 0x0004 BBA_RTK_NWAY_TEST_AUTO_PARALLEL_DET_FAULT = 0x0002 BBA_RTK_NWAY_TEST_AUTO_LINK_STATUS = 0x0001 BBA_RTK_RX_ER_COUNT = 0x72 BBA_RTK_CS_CFG = 0x74 BBA_RTK_CS_CFG_TESTFUN = 0x8000 ; 0x7c00 reserved BBA_RTK_CS_CFG_TPI_DISABLE = 0x0200 BBA_RTK_CS_CFG_HEARTBEAT = 0x0100 BBA_RTK_CS_CFG_JABBER = 0x0080 BBA_RTK_CS_CFG_FORCE_100LINK = 0x0040 BBA_RTK_CS_CFG_FORCE_CONNECT = 0x0020 ; 0x0010 reserved BBA_RTK_CS_CFG_LINK_GOOD = 0x0008 BBA_RTK_CS_CFG_LED1_LINK = 0x0004 ; 0x0002 reserved BBA_RTK_CS_CFG_BYP_SCRAMBLE = 0x0001 BBA_RTK_PHY_PAR_1 = 0x78 BBA_RTK_TWISTER_PAR = 0x7c BBA_RTK_PHY_PAR_2 = 0x80 BBA_RTK_PM_CRC = 0x84 ; first of 8 BBA_RTK_PM_WAKEUP = 0x8c ; first of 8 BBA_RTK_WAKEUP_MASK_LSB = 0xcc ; first of 8 BBA_RTK_FLASH_RW = 0xd4 BBA_RTK_FLASH_RW_FLASH_DATA_SHIFT = 24 BBA_RTK_FLASH_RW_FLASH_DATA_BITS = 4 BBA_RTK_FLASH_RW_FLASH_DATA_MASK = 0xf ; 0x00e00000 reserved BBA_RTK_FLASH_RW_ROM_CHIPSEL = 0x00100000 BBA_RTK_FLASH_RW_OUTPUT_ENB = 0x00080000 BBA_RTK_FLASH_RW_WRITE_ENB = 0x00040000 BBA_RTK_FLASH_RW_ACCESS_ENB = 0x00020000 BBA_RTK_FLASH_RW_FLASH_ADDR_SHIFT = 0 BBA_RTK_FLASH_RW_FLASH_ADDR_BITS = 17 BBA_RTK_FLASH_RW_FLASH_ADDR_MASK = 0x1ffff BBA_RTK_CFG5 = 0xd8 ; 0x80 reserved BBA_RTK_CFG5_BCAST_WAKE_ENB = 0x40 BBA_RTK_CFG5_MCAST_WAKE_ENB = 0x20 BBA_RTK_CFG5_UCAST_WAKT_ENB = 0x10 BBA_RTK_CFG5_FIFO_TEST = 0x08 BBA_RTK_CFG5_NO_AUTO_POWERDOWN = 0x04 BBA_RTK_CFG5_LANWAKE_ENB = 0x02 BBA_RTK_CFG5_PME_PCI_RESET = 0x01 BBA_RTK_FXN_EVENT = 0xf0 ; 0xffff0000 reserved BBA_RTK_FXN_EVENT_INTR = 0x00008000 ; 0x00007fe0 reserved BBA_RTK_FXN_EVENT_GWAKE = 0x00000010 ; 0x0000000f reserved BBA_RTK_FXN_EVENT_MASK = 0xf4 ; 0xffff0000 reserved BBA_RTK_FXN_EVENT_MASK_INTR = 0x00008000 BBA_RTK_FXN_EVENT_MASK_WAKEUP = 0x00004000 ; 0x00003fe0 reseved BBA_RTK_FXN_EVENT_MASK_GWAKE = 0x00000010 ; 0x0000000f reserved BBA_RTK_FXN_PRESENT_STATE = 0xf8 ; 0xffff0000 reserved BBA_RTK_FXN_PRESENT_STATE_INTR = 0x00008000 ; 0x00007fe0 reserved BBA_RTK_FXN_PRESENT_STATE_WAKE = 0x00000010 ; 0x0000000f reserved BBA_RTK_FXN_FORCE_EVENT = 0xfc ; 0xffff0000 reserved BBA_RTK_FXN_FORCE_EVENT_INTR = 0x00008000 ; 0x00007fe0 reserved BBA_RTK_FXN_FORCE_EVENT_WAKE = 0x00000010 ; 0x0000000f reserved ; Bits in RX status in packet header. These correspond to PDF section ; 6.1, "Receive Status Register in Rx packet header"; it is not a ; register, despite being called that. BBA_RTK_RXSTAT_MCAST = 0x8000 BBA_RTK_RXSTAT_PHYS = 0x4000 BBA_RTK_RXSTAT_BCAST = 0x2000 ; 0x1fc0 reserved BBA_RTK_RXSTAT_BADSYM = 0x0020 BBA_RTK_RXSTAT_RUNT = 0x0010 BBA_RTK_RXSTAT_GIANT = 0x0008 BBA_RTK_RXSTAT_BADCRC = 0x0004 BBA_RTK_RXSTAT_FRAME = 0x0002 BBA_RTK_RXSTAT_RXOK = 0x0001 .list pop