.list push off SCIF_BASE = 0xffe80000 SCSMR2 = 0xffe80000 ; page 560 SCSMR2_CHR = 0x0040 ; character size SCSMR2_CHR_8 = 0x0000 ; 8 bits SCSMR2_CHR_7 = 0x0040 ; 7 bits SCSMR2_PE = 0x0020 ; parity generation/checking SCSMR2_PE_DIS = 0x0000 ; disabled SCSMR2_PE_ENB = 0x0020 ; enabled SCSMR2_OE = 0x0010 ; parity odd or even SCSMR2_OE_E = 0x0000 ; even SCSMR2_OE_O = 0x0010 ; odd SCSMR2_STOP = 0x0008 ; stop bit count SCSMR2_STOP_1 = 0x0000 ; 1 SCSMR2_STOP_2 = 0x0008 ; 2 SCSMR2_CKS = 0x0003 ; clock divisor SCSMR2_CKS_DIV1 = 0x0000 ; ÷1 SCSMR2_CKS_DIV4 = 0x0001 ; ÷4 SCSMR2_CKS_DIV16 = 0x0002 ; ÷16 SCSMR2_CKS_DIV64 = 0x0003 ; ÷64 SCBRR2 = 0xffe80004 ; page 572 SCSCR2 = 0xffe80008 ; page 562 SCSCR2_TIE = 0x0080 ; xmit interrupt enable SCSCR2_RIE = 0x0040 ; recv interrupt enable SCSCR2_TE = 0x0020 ; transmitter enable SCSCR2_RE = 0x0010 ; receiver enable SCSCR2_REIE = 0x0008 ; recv error interrupt enable SCSCR2_CKE1 = 0x0002 ; clock select SCSCR2_CKE1_INT = 0x0000 ; internal SCSCR2_CKE1_EXT = 0x0002 ; external SCFTDR2 = 0xffe8000c ; page 559 SCFSR2 = 0xffe80010 ; page 565 SCFSR2_PER_SHIFT = 12 ; count of paity errors in FIFO SCFSR2_PER_BITS = 4 SCFSR2_PER_MASK = 0xf SCFSR2_FER_SHIFT = 8 ; count of framing errors in FIFO SCFSR2_FER_BITS = 4 SCFSR2_FER_MASK = 0xf SCFSR2_ER = 0x0080 ; receive error indication SCFSR2_TEND = 0x0040 ; xmit fifo fully drained SCFSR2_TDFE = 0x0020 ; xmit fifo drained to threshold SCFSR2_BRK = 0x0010 ; break detected SCFSR2_FER = 0x0008 ; framing error in head of recv FIFO SCFSR2_PER = 0x0004 ; parity error in head of recv FIFO SCFSR2_RDF = 0x0002 ; recv FIFO filled to threshold SCFSR2_DR = 0x0001 ; recv FIFO nonempty and line idle SCFRDR2 = 0xffe80014 ; page 558 SCFCR2 = 0xffe80018 ; page 573 SCFCR2_RXT = 0x00c0 ; recv FIFO threshold SCFCR2_RXT_1 = 0x0000 ; interrupt at 1 byte SCFCR2_RXT_4 = 0x0040 ; interrupt at 4 byte SCFCR2_RXT_8 = 0x0080 ; interrupt at 8 byte SCFCR2_RXT_14 = 0x00c0 ; interrupt at 14 bytes SCFCR2_TXT = 0x0030 ; xmit FIFO threshold SCFCR2_TXT_8 = 0x0000 ; interrupt when 8 left to send SCFCR2_TXT_4 = 0x0010 ; interrupt when 4 left to send SCFCR2_TXT_2 = 0x0020 ; interrupt when 2 left to send SCFCR2_TXT_1 = 0x0030 ; interrupt when 1 left to send SCFCR2_MCE = 0x0008 ; RTS/CTS enable SCFCR2_TFRST = 0x0004 ; reset xmit FIFO SCFCR2_RFRST = 0x0002 ; reset recv FIFO SCFCR2_LOOP = 0x0001 ; internal loopback SCFDR2 = 0xffe8001c ; page 575 SCFDR2_TX_SHIFT = 8 ; TX FIFO fill count SCFDR2_TX_BITS = 5 SCFDR2_TX_MASK = 0x1f SCFDR2_RX_SHIFT = 0 ; RX FIFO fill count SCFDR2_RX_BITS = 5 SCFDR2_RX_MASK = 0x1f SCSPTR2 = 0xffe80020 ; page 576 SCPTR2_RTSIO = 0x0080 ; RTS direction SCPTR2_RTSIO_I = 0x0000 ; input SCPTR2_RTSIO_O = 0x0080 ; output (MCE should be 0) SCPTR2_RTSDT = 0x0040 ; RTS data SCPTR2_CTSIO = 0x0020 ; CTS direction SCPTR2_CTSIO_I = 0x0000 ; input SCPTR2_CTSIO_O = 0x0020 ; output (MCE should be 0) SCPTR2_CTSDT = 0x0010 ; CTS data SCPTR2_SPB2IO = 0x0002 ; BREAK TXD override enable (clear TE when set) SCPTR2_SPB2DT = 0x0001 ; BREAK TXD override data SCLSR2 = 0xffe80024 ; page 581 SCLSR2_ORER = 0x0001 ; recv FIFO overrun .list pop