.list push off BBA_BASE = 0xa1001700 ; The chip in the BBA - in my BBA, at least - is labeled ; ; RTL8139C ; 19213Q1 ; Here's what the 8139c PDF, run through pdftotext, says. This PDF is ; the one from http://realtek.info/pdf/rtl8139c.pdf; Realtek's own doc ; is, as far as I can tell from my minimal Web skillz on their ; webpages, NDAed. Perhaps they're too ashamed of their design to ; admit to the world how crappy it is? ; I've reformatted this text a bit. ; 0000 R/W IDR0 ID Register 0: The ID registers 0-5 are ; only permitted to read/write by 4-byte ; access. Read access can be byte, word, ; or double word access. The initial ; value is autoloaded from the EEPROM ; EthernetID field. ; 0001 R/W IDR1 ID Register 1 ; 0002 R/W IDR2 ID Register 2 ; 0003 R/W IDR3 ID Register 3 ; 0004 R/W IDR4 ID Register 4 ; 0005 R/W IDR5 ID Register 5 ; 0006-0007 - - Reserved ; 0008 R/W MAR0 Multicast Register 0: The MAR registers ; 0-7 are only permitted to read/write by ; 4-byte access. Read access can be ; byte, word, or double word access. ; Driver is responsible for initializing ; these registers. ; 0009 R/W MAR1 Multicast Register 1 ; 000A R/W MAR2 Multicast Register 2 ; 000B R/W MAR3 Multicast Register 3 ; 000C R/W MAR4 Multicast Register 4 ; 000D R/W MAR5 Multicast Register 5 ; 000E R/W MAR6 Multicast Register 6 ; 000F R/W MAR7 Multicast Register 7 ; 0010-0013 R/W TSD0 Transmit Status of Descriptor 0 ; 0014-0017 R/W TSD1 Transmit Status of Descriptor 1 ; 0018-001B R/W TSD2 Transmit Status of Descriptor 2 ; 001C-001F R/W TSD3 Transmit Status of Descriptor 3 ; 0020-0023 R/W TSAD0 Transmit Start Address of Descriptor0 ; 0024-0027 R/W TSAD1 Transmit Start Address of Descriptor1 ; 0028-002B R/W TSAD2 Transmit Start Address of Descriptor2 ; 002C-002F R/W TSAD3 Transmit Start Address of Descriptor3 ; 0030-0033 R/W RBSTART Receive (Rx) Buffer Start Address ; 0034-0035 R ERBCR Early Receive (Rx) Byte Count Register ; 0036 R ERSR Early Rx Status Register ; 0037 R/W CR Command Register ; 0038-0039 R/W CAPR Current Address of Packet Read (initial ; value is 0FFF0) ; 003A-003B R CBR Current Buffer Address: The initial ; value is 0000. It reflects total ; received byte-count in the rx buffer. ; 003C-003D R/W IMR Interrupt Mask Register ; 003E-003F R/W ISR Interrupt Status Register ; 0040-0043 R/W TCR Transmit (Tx) Configuration Register ; 0044-0047 R/W RCR Receive (Rx) Configuration Register ; 0048-004B R/W TCTR Timer Count Register: This register ; contains a 32-bit general-purpose ; timer. Writing any value to this ; 32-bit register will reset the original ; timer and begin to count from zero. ; 004C-004F R/W MPC Missed Packet Counter: Indicates the ; number of packets discarded due to rx ; FIFO overflow. It is a 24-bit counter. ; After s/w reset, MPC is cleared. Only ; the lower 3 bytes are valid. When any ; value is written, MPC will be reset ; also. ; 0050 R/W 9346CR 93C46 (93C56) Command Register ; 0051 R/W CONFIG0 Configuration Register 0 ; 0052 R/W CONFIG1 Configuration Register 1 ; 0053 - - Reserved ; 0054-0057 R/W TimerInt Timer Interrupt Register: Once having ; written a nonzero value to this ; register, the Timeout bit of ISR ; register will be set whenever the TCTR ; reaches to this value. The Timeout bit ; will never be set as long as TimerInt ; register is zero. ; 0058 R/W MSR Media Status Register ; 0059 R/W CONFIG3 Configuration register 3 ; 005A R/W CONFIG4 Configuration register 4 ; 005B - - Reserved ; 005C-005D R/W MULINT Multiple Interrupt Select ; 005E R RERID PCI Revision ID = 10h ; 005F - - Reserved ; 0060-0061 R TSAD Transmit Status of All Descriptors ; 0062-0063 R/W BMCR Basic Mode Control Register ; 0064-0065 R BMSR Basic Mode Status Register ; 0066-0067 R/W ANAR Auto-Negotiation Advertisement Register ; 0068-0069 R ANLPAR Auto-Negotiation Link Partner Register ; 006A-006B R ANER Auto-Negotiation Expansion Register ; 006C-006D R DIS Disconnect Counter ; 006E-006F R FCSC False Carrier Sense Counter ; 0070-0071 R/W NWAYTR N-way Test Register ; 0072-0073 R REC RX_ER Counter ; 0074-0075 R/W CSCR CS Configuration Register ; 0076-0077 - - Reserved ; 0078-007B R/W PHY1_PARM PHY parameter 1 ; 007C-007F R/W TW_PARM Twister parameter ; 0080 R/W PHY2_PARM PHY parameter 2 ; 0081-0083 - - Reserved ; 0084 R/W CRC0 Power Management CRC Register0 for Wakeup Frame0 ; 0085 R/W CRC1 Power Management CRC Register1 for Wakeup Frame1 ; 0086 R/W CRC2 Power Management CRC Register2 for Wakeup Frame2 ; 0087 R/W CRC3 Power Management CRC Register3 for Wakeup Frame3 ; 0088 R/W CRC4 Power Management CRC Register4 for Wakeup Frame4 ; 0089 R/W CRC5 Power Management CRC Register5 for Wakeup Frame5 ; 008A R/W CRC6 Power Management CRC Register6 for Wakeup Frame6 ; 008B R/W CRC7 Power Management CRC Register7 for Wakeup Frame7 ; 008C­0093 R/W Wakeup0 Power Management Wakeup Frame0 (64bit) ; 0094­009B R/W Wakeup1 Power Management Wakeup Frame1 (64bit) ; 009C­00A3 R/W Wakeup2 Power Management Wakeup Frame2 (64bit) ; 00A4­00AB R/W Wakeup3 Power Management Wakeup Frame3 (64bit) ; 00AC­00B3 R/W Wakeup4 Power Management Wakeup Frame4 (64bit) ; 00B4­00BB R/W Wakeup5 Power Management Wakeup Frame5 (64bit) ; 00BC­00C3 R/W Wakeup6 Power Management Wakeup Frame6 (64bit) ; 00C4­00CB R/W Wakeup7 Power Management Wakeup Frame7 (64bit) ; 00CC R/W LSBCRC0 LSB of the Mask byte of Wakeup Frame0 Within Offset 12 to 75 ; 00CD R/W LSBCRC1 LSB of the Mask byte of Wakeup Frame1 Within Offset 12 to 75 ; 00CE R/W LSBCRC2 LSB of the Mask byte of Wakeup Frame2 Within Offset 12 to 75 ; 00CF R/W LSBCRC3 LSB of the Mask byte of Wakeup Frame3 Within Offset 12 to 75 ; 00D0 R/W LSBCRC4 LSB of the Mask byte of Wakeup Frame4 Within Offset 12 to 75 ; 00D1 R/W LSBCRC5 LSB of the Mask byte of Wakeup Frame5 Within Offset 12 to 75 ; 00D2 R/W LSBCRC6 LSB of the Mask byte of Wakeup Frame6 Within Offset 12 to 75 ; 00D3 R/W LSBCRC7 LSB of the Mask byte of Wakeup Frame7 Within Offset 12 to 75 ; 00D4-00D7 R/W FLASH Flash Memory Read/Write Register ; 00D8 R/W Config5 Configuration Register 5 ; 00D9-00EF - - Reserved ; 00F0-00F3 R/W FER Function Event Register (Cardbus only) ; 00F4-00F7 R/W FEMR Function Event Mask Register (CardBus only) ; 00F8-00FB R FPSR Function Present State Register (CardBus only) ; 00FC-00FF W FFER Function Force Event Register (CardBus only) BBA_RTK_MAC = 0x00 ; first of 6 BBA_RTK_MULTI_FILTER = 0x08 ; first of 8 BBA_RTK_TXSTAT = 0x10 ; first of 4 BBA_RTK_TXSTAT_LOST_CARRIER = 0x80000000 BBA_RTK_TXSTAT_ABORTED = 0x40000000 BBA_RTK_TXSTAT_LATE_COLL = 0x20000000 BBA_RTK_TXSTAT_HEARTBEAT = 0x10000000 BBA_RTK_TXSTAT_NCOLL_SHIFT = 24 BBA_RTK_TXSTAT_NCOLL_MASK = 0xf BBA_RTK_TXSTAT_EARLYTXTHRESH_SHIFT = 16 BBA_RTK_TXSTAT_EARLYTXTHRESH_MASK = 0x3f BBA_RTK_TXSTAT_TXOK = 0x00008000 BBA_RTK_TXSTAT_UNDERRUN = 0x00004000 BBA_RTK_TXSTAT_OWN = 0x00002000 BBA_RTK_TXSTAT_SIZE_SHIFT = 0 BBA_RTK_TXSTAT_SIZE_MASK = 0x1fff BBA_RTK_TXADDR = 0x20 ; first of 4 BBA_RTK_RXSTART = 0x30 BBA_RTK_EARLY_RX_COUNT = 0x34 BBA_RTK_EARLY_RX_STAT = 0x36 BBA_RTK_EARLY_RX_STAT_GOOD = 0x08 BBA_RTK_EARLY_RX_STAT_BAD = 0x04 BBA_RTK_EARLY_RX_STAT_OVERWRITE = 0x02 BBA_RTK_EARLY_RX_STAT_OK = 0x01 BBA_RTK_COMMAND = 0x37 BBA_RTK_COMMAND_RESET = 0x10 BBA_RTK_COMMAND_ENABLE_RX = 0x08 BBA_RTK_COMMAND_ENABLE_TX = 0x04 BBA_RTK_COMMAND_RXBUF_EMPTY = 0x01 BBA_RTK_CUR_PKT_READ = 0x38 BBA_RTK_CUR_RX_PTR = 0x3a BBA_RTK_INTR_MASK = 0x3c BBA_RTK_INTR_MASK_SYSERR = 0x8000 BBA_RTK_INTR_MASK_TIMEOUT = 0x4000 BBA_RTK_INTR_MASK_LENCHG = 0x2000 BBA_RTK_INTR_MASK_RXFOVF = 0x0040 BBA_RTK_INTR_MASK_UND_LINK = 0x0020 BBA_RTK_INTR_MASK_RXBOVF = 0x0010 BBA_RTK_INTR_MASK_TXERR = 0x0008 BBA_RTK_INTR_MASK_TXOK = 0x0004 BBA_RTK_INTR_MASK_RXERR = 0x0002 BBA_RTK_INTR_MASK_RXOK = 0x0001 BBA_RTK_INTR_STAT = 0x3e BBA_RTK_INTR_STAT_ BBA_RTK_TXCFG = 0x40 BBA_RTK_TXCFG_CLRABRT = 0x00000001 ; clear abort, retransmit pkt BBA_RTK_TXCFG_MAXDMA_BITS = 3 ; DMA burst size BBA_RTK_TXCFG_MAXDMA_SHIFT = 8 ; value is lg(size)-4: BBA_RTK_TXCFG_MAXDMA_16 = 0 BBA_RTK_TXCFG_MAXDMA_32 = 1 BBA_RTK_TXCFG_MAXDMA_64 = 2 BBA_RTK_TXCFG_MAXDMA_128 = 3 BBA_RTK_TXCFG_MAXDMA_256 = 4 BBA_RTK_TXCFG_MAXDMA_512 = 5 BBA_RTK_TXCFG_MAXDMA_1024 = 6 BBA_RTK_TXCFG_MAXDMA_2048 = 7 BBA_RTK_TXCFG_CRCAPPEND = 0x00010000 ; append CRC to packets (0 = yes) BBA_RTK_TXCFG_LOOPBKTST = 0x00060000 ; loopback test mdoe BBA_RTK_TXCFG_IFG2 = 0x00080000 ; "8169 only" - NetBSD BBA_RTK_TXCFG_IFG_BITS = 2 ; interframe gap BBA_RTK_TXCFG_IFG_SHIFT = 24 BBA_RTK_TXCFG_HWREV = 0x7CC00000 BBA_RTK_RXCFG = 0x44 BBA_RTK_RXCFG_RX_PROMISC = 0x00000001 BBA_RTK_RXCFG_RX_INDIVIDUAL = 0x00000002 BBA_RTK_RXCFG_RX_ALL_MULTI = 0x00000004 BBA_RTK_RXCFG_RX_ALL_BCAST = 0x00000008 BBA_RTK_RXCFG_RX_RUNT = 0x00000010 BBA_RTK_RXCFG_RX_ERRORS = 0x00000020 BBA_RTK_RXCFG_WRAP = 0x00000080 BBA_RTK_RXCFG_MAXDMA_BITS = 3 BBA_RTK_RXCFG_MAXDMA_SHIFT = 8 BBA_RTK_RXCFG_MAXDMA_16 = 0 BBA_RTK_RXCFG_MAXDMA_32 = 1 BBA_RTK_RXCFG_MAXDMA_64 = 2 BBA_RTK_RXCFG_MAXDMA_128 = 3 BBA_RTK_RXCFG_MAXDMA_256 = 4 BBA_RTK_RXCFG_MAXDMA_512 = 5 BBA_RTK_RXCFG_MAXDMA_1024 = 6 BBA_RTK_RXCFG_MAXDMA_INF = 7 BBA_RTK_RXCFG_BUFSIZ_BITS = 2 BBA_RTK_RXCFG_BUFSIZ_SHIFT = 11 BBA_RTK_RXCFG_BUFSIZ_8K = 0 BBA_RTK_RXCFG_BUFSIZ_16K = 1 BBA_RTK_RXCFG_BUFSIZ_32K = 2 BBA_RTK_RXCFG_BUFSIZ_64K = 3 BBA_RTK_RXCFG_FIFOTHRESH_BITS = 3 BBA_RTK_RXCFG_FIFOTHRESH_SHIFT = 13 BBA_RTK_RXCFG_FIFOTHRESH_16 = 0 BBA_RTK_RXCFG_FIFOTHRESH_32 = 1 BBA_RTK_RXCFG_FIFOTHRESH_64 = 2 BBA_RTK_RXCFG_FIFOTHRESH_128 = 3 BBA_RTK_RXCFG_FIFOTHRESH_256 = 4 BBA_RTK_RXCFG_FIFOTHRESH_512 = 5 BBA_RTK_RXCFG_FIFOTHRESH_1024 = 6 BBA_RTK_RXCFG_FIFOTHRESH_INF = 7 BBA_RTK_RXCFG_EARLYTHRESH_BITS = 3 BBA_RTK_RXCFG_EARLYTHRESH_SHIFT = 24 BBA_RTK_TIMER_COUNT = 0x48 BBA_RTK_MISS_COUNT = 0x4c BBA_RTK_EECMD = 0x50 BBA_RTK_EECMD_UNLOCK = 0xc0 BBA_RTK_CFG0 = 0x51 BBA_RTK_CFG0_ROM0 = 0x01 ; ??? BBA_RTK_CFG0_ROM1 = 0x02 ; ??? BBA_RTK_CFG0_ROM2 = 0x04 ; ??? BBA_RTK_CFG0_PL0 = 0x08 ; ??? BBA_RTK_CFG0_PL1 = 0x10 ; ??? BBA_RTK_CFG0_10MBPS = 0x20 ; "10 Mbps internal mode" - NetBSD BBA_RTK_CFG0_PCS = 0x40 ; ??? BBA_RTK_CFG0_SCR = 0x80 ; ??? BBA_RTK_CFG1 = 0x52 BBA_RTK_CFG1_POWER_DOWN = 0x01 ; "Cfg1_PM_Enable" - libronin, "RTK_CFG_PWRDWN" - NetBSD BBA_RTK_CFG1_SLEEP = 0x02 ; "Cfg1_VPD_Enable" - libronin, "RTK_CFG_SLEEP" - NetBSD BBA_RTK_CFG1_IOMAP = 0x04 ; "Cfg1_PIO" - libronin, "RTK_CFG1_IOMAP" - NetBSD BBA_RTK_CFG1_MEMMAP = 0x08 ; "Cfg1_MMIO" - libronin, "RTK_CFG1_MEMMAP" - NetBSD BBA_RTK_CFG1_RSVD = 0x10 ; "Cfg1_LWAKE" - libronin, "RTK_CFG1_RSVD" - NetBSD BBA_RTK_CFG1_DRVLOAD = 0x20 ; "Cfg1_Driver_Load" - libronin, "RTK_CFG1_DRVLOAD" - NetBSD BBA_RTK_CFG1_LED0 = 0x40 ; libronin and NetBSD agree BBA_RTK_CFG1_FULLDUPLEX = 0x40 ; "8129 only" - NetBSD BBA_RTK_CFG1_LED1 = 0x80 ; libronin and NetBSD agree BBA_RTK_TIMER_INT = 0x54 BBA_RTK_MEDIA_STATUS = 0x58 BBA_RTK_CFG3 = 0x59 BBA_RTK_CFG4 = 0x5a BBA_RTK_MULTI_INTR = 0x5c BBA_RTK_PCI_REV_ID = 0x5e BBA_RTK_TX_STATUS_ALL = 0x60 BBA_RTK_BASIC_MODE_CTL = 0x62 BBA_RTK_BASIC_MODE_STAT = 0x64 BBA_RTK_AUTONEG_ADV = 0x66 BBA_RTK_AUTONEG_PARTNER = 0x68 BBA_RTK_AUTONEG_EXP = 0x6a BBA_RTK_DISCONNECTS = 0x6c BBA_RTK_FALSE_CARRIER = 0x6e BBA_RTK_NWAY_TEST = 0x70 BBA_RTK_RX_ER_COUNT = 0x72 BBA_RTK_CS_CFG = 0x74 BBA_RTK_PHY_PAR_1 = 0x78 BBA_RTK_TWISTER_PAR = 0x7c BBA_RTK_PHY_PAR_2 = 0x80 BBA_RTK_PM_CRC = 0x84 ; first of 8 BBA_RTK_PM_WAKEUP = 0x8c ; first of 8 BBA_RTK_WAKEUP_MASK_LSB = 0xcc ; first of 8 BBA_RTK_FLASH_RW = 0xd4 BBA_RTK_CFG5 = 0xd8 BBA_RTK_FXN_EVENT = 0xf0 BBA_RTK_FXN_EVENT_MASK = 0xf4 BBA_RTK_FXN_PRESENT_STATE = 0xf8 BBA_RTK_FXN_FORCE_EVENT = 0xfc ; Bits in RX status in packet header. These bits may be in reversed ; order; doc uses bit numbers, not mask values. BBA_RTK_RXSTAT_MCAST = 0x8000 BBA_RTK_RXSTAT_PHYS = 0x4000 BBA_RTK_RXSTAT_BCAST = 0x2000 BBA_RTK_RXSTAT_BADSYM = 0x0020 BBA_RTK_RXSTAT_RUNT = 0x0010 BBA_RTK_RXSTAT_GIANT = 0x0008 BBA_RTK_RXSTAT_BADCRC = 0x0004 BBA_RTK_RXSTAT_FRAME = 0x0002 BBA_RTK_RXSTAT_RXOK = 0x0001 .list pop