; This is designed to be serial-line downloaded to cdcode.
;
; Our memory map:
;
;	[8c000000,8c010000)	Stack (r15 set by cdcode)
;	[8c010000,8c01????)	cdcode
;	[8c020000,8c030000)	our data segment
;	[8c030000,8c03????)	our text segment

	.include "regs.s"

BUS_RESET = 0xa05f6c8c
BUS_RESET_VALUE = 0x6155404f
BUS_RESET2 = 0xa05f6c10
BUS_RESET2_VALUE = 0
BUS_DMAADDR = 0xa05f6c04
BUS_ENABLE = 0xa05f6c14
BUS_ENABLE_VALUE = 1
BUS_STATE = 0xa05f6c18
BUS_STATE_GO = 1
BUS_STATE_RUNNING = 1
BUS_SPEED = 0xa05f6c80
DMA_ADDRMASK = 0x1fffffe0
SPEED_TIMEOUT_SHIFT = 16
SPEED_2MBPS = 0
CMD_DEVINFO = 1
CMD_EXTINFO = 2
CMD_RESET = 3
CMD_SHUTDOWN = 4
RESP_DEVINFO = 5
RESP_EXTINFO = 6
RESP_ACK = 7
RESP_DATA = 8
CMD_GETCOND = 9
CMD_GETMEMINFO = 10
CMD_BLOCKREAD = 11
CMD_BLOCKWRITE = 12
CMD_SETCOND = 14
ERR_NORESP = [256-1]
ERR_FUNCUNSUPP = [256-2]
ERR_UNKCMD = [256-3]
ERR_SENDAGAIN = [256-4]
ERR_FILEERR = [256-5]
XDESC_LAST = 0x80000000
XDESC_PORTSHIFT = 16
XDESC_GUN = 0x00000200
XDESC_LENSHIFT = 0
; These shift values look backwards; this is because frames are big-endian.
FRAME_CRSHIFT = 0
FRAME_RSHIFT = 8
FRAME_SSHIFT = 16
FRAME_LENSHIFT = 24
ADDR_PORTSHIFT = 6
ADDR_MAIN = 0x20
ADDR_SUB5 = 0x10
ADDR_SUB4 = 0x08
ADDR_SUB3 = 0x04
ADDR_SUB2 = 0x02
ADDR_SUB1 = 0x01
	.macro	Frame	cr, rport, rbits, sport, sbits, len
	.long	[[$(cr)] << FRAME_CRSHIFT] | [[[[$(rport)] << ADDR_PORTSHIFT] | [$(rbits)]] << FRAME_RSHIFT] | [[[[$(sport)] << ADDR_PORTSHIFT] | [$(sbits)]] << FRAME_SSHIFT] | [[$(len)] << FRAME_LENSHIFT]
	.endm

. = 0x8c020000
	.align	32
cmds:
	.long	[0 << XDESC_PORTSHIFT] | [0 << XDESC_LENSHIFT]
	.long	resp0 & DMA_ADDRMASK
	Frame	CMD_DEVINFO, 0, ADDR_MAIN, 0, 0, 0
	.long	[1 << XDESC_PORTSHIFT] | [0 << XDESC_LENSHIFT]
	.long	resp1 & DMA_ADDRMASK
	Frame	CMD_DEVINFO, 1, ADDR_MAIN, 0, 0, 0
	.long	[2 << XDESC_PORTSHIFT] | [0 << XDESC_LENSHIFT]
	.long	resp2 & DMA_ADDRMASK
	Frame	CMD_DEVINFO, 2, ADDR_MAIN, 0, 0, 0
	.long	XDESC_LAST | [3 << XDESC_PORTSHIFT] | [0 << XDESC_LENSHIFT]
	.long	resp3 & DMA_ADDRMASK
	Frame	CMD_DEVINFO, 3, ADDR_MAIN, 0, 0, 0
	.align	32
respbeg:
resp0:
	.space	1024
resp1:
	.space	1024
resp2:
	.space	1024
resp3:
	.space	1024
respend:

. = 0x8c030000
; The only things startup.s sets up that cdcode hasn't already done for
;  us are (1) fpscr and (2) clearing bss.  We don't have bss because we
;  aren't linked by a conventional linker, and we don't use floating
;  point so we don't care about fpscr.  So we have nothing to do here.
;  Just dive straight into the code.
	bsr	putchar2
	 mov	#'a,r1
	bsr	init_hw
	 nop
	bsr	putchar2
	 mov	#'b,r1
	bsr	try_cmds
	 nop
	bsr	putchar2
	 mov	#'c,r1
	lds	r11,pr
	rts
	 nop

init_hw:
	mova	9f,r0
1:	mov.l	@r0+,r1
	tst	r1,r1
	bt	1f
	mov.l	@r0+,r2
	bra	1b
	 mov.l	r2,@r1
1:	rts
	 nop
	.align	4
9:	.long	BUS_RESET,	BUS_RESET_VALUE
	.long	BUS_RESET2,	BUS_RESET2_VALUE
	.long	BUS_SPEED,	SPEED_2MBPS|[50000<<SPEED_TIMEOUT_SHIFT]
	.long	BUS_ENABLE,	BUS_ENABLE_VALUE
	.long	0

try_cmds:
	sts.l	pr,@-r15
	SETS.L	#respbeg,r1
	SETS.L	#respend-respbeg,r2
	SETS.L	#0xd0,r0
	add	r2,r1
1:	mov.b	r0,@-r1
	dt	r2
	bf	1b
	bsr	flush_dcache
	 nop
	SETS.L	#BUS_DMAADDR,r1
	SETS.L	#cmds&DMA_ADDRMASK,r2
	mov.l	r2,@r1
	SETS.L	#BUS_STATE,r3
	SETS.L	#BUS_STATE_GO,r0
	mov.l	r0,@r3
1:	bsr	putchar
	 mov	#'.,r1
	mov.l	@r3,r0
	tst	#BUS_STATE_RUNNING,r0
	bf	1b
	lds.l	@r15+,pr
	rts
	 nop

flush_dcache:
	mova	1f,r0
	SETS.L	#Px_MASKOFF,r1
	SETS.L	#P2_BITS,r2
	and	r1,r0
	or	r2,r0
	jmp	@r0
	 nop
	.align	4
1:	SETS.L	#1<<DCAA_ENTRY_BITS,r5
	SETS.L	#~DCAA_U,r4
	SETS.L	#DCAA_BASE,r3
1:	mov.l	@r3,r0
	and	#DCAA_U|DCAA_V,r0
	cmp/eq	#DCAA_U|DCAA_V,r0
	bf	2f
	and	r4,r0
	mov.l	r4,@r3
2:	dt	r5
	bf/s	1b
	 add	#32,r3
	SETS.L	#CCR,r3
	SETS.L	#CCR_ICI,r4
	mov.l	@r3,r0
	or	r4,r0
	mov.l	r0,@r3
	nop			; #1
	nop			; #2
	nop			; #3
	nop			; #4
	nop			; #5
	nop			; #6
	nop			; #7
	nop			; #8
	rts
	 nop

printhex8:
	mov	#8,r0
printhexN:
	mov.l	r4,@-r15
	mov	r0,r4
	add	#-8,r0
	neg	r0,r0
	SHLL	#2,r0
	shld	r0,r1
	mov.l	r3,@-r15
	mov.l	r2,@-r15
	sts.l	pr,@-r15
	mova	9f,r0
	mov	r0,r3
	mov	r1,r2
1:	mov	r2,r0
	SHLR	#28,r0
	SHLL	#4,r2
	add	r3,r0
	bsr	putchar
	 mov.b	@r0,r1
	dt	r4
	bf	1b
	lds.l	@r15+,pr
	mov.l	@r15+,r2
	mov.l	@r15+,r3
	rts
	 mov.l	@r15+,r4
	.align	4
9:	.ascii	"0123456789abcdef"
	.align	2

putchar2:
	sts.l	pr,@-r15
	bsr	putchar
	 mov.l	r1,@-r15
	mov.l	@r15+,r1
	 lds.l	@r15+,pr
putchar:
	ldc	r14,gbr
1:	mov.w	@(SCFDR2-SCIF_BASE,gbr),r0
	SHXR	#SCFDR2_TX_SHIFT,r0
	and	#SCFDR2_TX_MASK,r0
	cmp/eq	#16,r0
	bt	1b
	mov	r1,r0
	mov.b	r0,@(SCFTDR2-SCIF_BASE,gbr)
1:	mov.w	@(SCFDR2-SCIF_BASE,gbr),r0
	SHXR	#SCFDR2_TX_SHIFT,r0
	tst	#SCFDR2_TX_MASK,r0
	bf	1b
	rts
	 nop

	SETCONST

.if 0

1c210005

01000000 - func (controller only)
fe060f00 - controller function_data
00000000 - unused
00000000 - unused
      ff - area code
    00   - connector direction
7244     - product name ("Dreamcast Controller          ")
636d6165
20747361
746e6f43
6c6c6f72
20207265
20202020
20202020
646f7250 - product license ("Produced By or Under License From SEGA ENTERPRISES,LTD.     ")
64656375
20794220
5520726f
7265646e
63694c20
65736e65
6f724620
4553206d
45204147
5245544e
53495250
4c2c5345
202e4454
20202020
01ae     - standby power (430)
01f4     - max power (500)

.endif