PSR:
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
| impl  |  ver  |  icc  | reserved  |C|F|  PIL  |S|P|T|   CWP   |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
impl = implementation number, not modifiable
ver = constant, meaning depends on impl, not modifiable
icc = integer condition codes, modified by xxxcc (eg andcc), and wrpsr
	+-+-+-+-+
	|N|Z|V|C|
	+-+-+-+-+
	N = negative
	Z = zero
	V = overflow
	C = carry
reserved = always write as 0s
C = coprocessor enable
F = FPU enable
PIL = current interrupt level
S = supervisor mode
P = copy of S as of most recent trap
T = trap enable
CWP = current window pointer

WIM: 32-bit mask, one bit per window.  Attempting to save or
restore/rett into a window whose bit is set takes a window overflow or
underflow trap.

TBR: 32-bit register.  Top 20 bits [31:12] contain address of trap
vector table (must be on a 4K boundary).  Next 8 bits store offset into
trap table, set by processor at trap time; they cannot be modified by
wrtbr.  Low four bits are stuck zero.

FSR:
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|RD |RP |   TEM   | reserved  | ftt |q|r|fcc|  aexc   |  cexc   |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
RD = rounding direction:
	00 = nearest
	01 = zero
	10 = positive infinity
	11 = negative infinity
RP = rounding precision:
	00 = extended
	01 = single
	10 = double
	11 = (unused)
TEM = trap enable mask, bits match cexc bits
reserved = read as 0s, always write as 0s
ftt = FPU trap type (read-only), written by processor when taking
	fp_exception, valid until next FPop completes
	0 = none
	1 = IEEE exception
	2 = unfinished FPop
	3 = unimplemented FPop
	4 = sequence error
q = queue not empty (read-only)
r = reserved, read as 0, always write as 0
fcc = FPU condition codes:
	0 = fs1 = fs2
	1 = fs1 < fs2
	1 = fs1 > fs2
	1 = fs1 ? fs2 (unordered)
aexc = accrued exception: as each FPop completes, if TEM&cexc != 0, an
	exception is generated, otherwise aexc |= cexc.  Modifiable.
cexc = current exception: as each FPop completes, cexc holds any
	exceptions it generated:
	+-+-+-+-+-+
	|V|O|U|D|X|
	+-+-+-+-+-+
	V = invalid (eg, 0/0 or infinity-infinity)
	O = overflow
	U = underflow
	D = division by zero (but not 0/0)
	X = inexact

Instruction formats:

Format 1:
+-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-+
|opc|                       displacement                        |
+-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-+

Format 2:
+-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-+
|opc|  dreg   | op2 |              immediate data               |
+-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-+
|opc|a| cond  | op2 |               displacement                |
+-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-+

Format 3:
+-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-+
|opc|  dreg   |    op3    |  sreg1  |i|      asi      |  sreg2  |
+-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-+
|opc|  dreg   |    op3    |  sreg1  |i|     immediate data      |
+-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-+
|opc|  dreg   |    op3    |  sreg1  |       opf       |  sreg2  |
+-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-|-+-+-+-*-+-+-+-+

opc = selects format:
	00 = format 2
	01 = format 1
	1x = format 3
op2 = selects operation:
	000 = unimpl
	010 = b<icc>
	100 = sethi
	110 = fb<fcc>
	111 = cb<ccc>
dreg = destination register (source register for stores)
a = annul bit, for branches
cond = condition selection bits for branches
displacement = sign-extended displacement, implicitly multiplied by 4
op3 = selects operation: see below
i = selects second operand for non-FP instructions:
	0 = operand is register #sreg2
	1 = operand is immediate data
asi = alternative address space identifier (for load/store alternate)
sreg1 = source register 1 number
sreg2 = source register 2 number
opf = operation specifier for FP instructions

ASIs:
	0-7	implementation definable
	8	user instruction
	9	supervisor instruction
	10	user data
	11	supervisor data
	12-255	implementation definable

Instructions:
(* = privileged)
(op2=xxx means 00 in opc bits, xxx in op2 bits)
(op3=xx/yyyyyy means xx in opc bits, yyyyyy in op3 bits)
(opf=x/yyyyyyyyy means 10 in opc, 11010x in op3, yyyyyyyyy in opf)
r<x> = integer register #<x>
f<x> = fpu register #<x>
c<x> = coprocessor register #<x>
simm13 = signed "immediate data" in format 3 instructions (13 bits)
const22 = "immediate data" in format 2 instructions (22 bits)
asi = alternative address space indicator in format 3 instructions (0-255)
[rfc]s1 = [rfc]<sreg1>
[rfc]s2 = [rfc]<sreg2>
[rfc]d = [rfc]<dreg>
regaddr =
	rs1
	rs1 + rs2
address =
	rs1
	rs1 + rs2
	rs1 + simm13
	rs1 - simm13
	simm13
	simm13 + rs1
reg/imm =
	rs2
	simm13

ldsb	op3=11/001001	ldsb	[address], rd
ldsh	op3=11/001010	ldsh	[address], rd
ldub	op3=11/000001	ldub	[address], rd
lduh	op3=11/000010	lduh	[address], rd
ld	op3=11/000000	ld	[address], rd
ldd	op3=11/000011	ldd	[address], rd
	load from rs1+rs2 (i=0) or rs1+simm13 (i=1)
	ldd ignores low bit of dreg, writes MS half in even reg, LS in odd

ldsba	op3=11/011001*	ldsba	[regaddr] asi, rd
ldsha	op3=11/011010*	ldsha	[regaddr] asi, rd
lduba	op3=11/010001*	lduba	[regaddr] asi, rd
lduha	op3=11/010010*	lduha	[regaddr] asi, rd
lda	op3=11/010000*	lda	[regaddr] asi, rd
ldda	op3=11/010011*	ldda	[regaddr] asi, rd
	load from rs1+rs2 (i=0) or take illegal instruction trap (i=1)
	ldda ignores low bit of dreg, writes MS half in even reg, LS in odd

ldf	op3=11/100000	ld	[address], fd
lddf	op3=11/100011	ldd	[address], fd
ldfsr	op3=11/100001	ld	[address], %fsr
	load from rs1+rs2 (i=0) or rs1+simm13 (i=1)
	ldd ignores low bit of dreg, writes MS half in even reg, LS in odd

ldc	op3=11/110000	ld	[address], cd
lddc	op3=11/110011	ldd	[address], cd
ldcsr	op3=11/110001	ld	[address], %csr
	load from rs1+rs2 (i=0) or rs1+simm13 (i=1)
	ldd ignores low bit of dreg, writes MS half in even reg, LS in odd

stb	op3=11/000101	stb	rd, [address] (syn: stub, stsb)
sth	op3=11/000110	sth	rd, [address] (syn: stuh, stsh)
st	op3=11/000100	st	rd, [address]
std	op3=11/000111	std	rd, [address]
	store into rs1+rs2 (i=0) or rs1+simm13 (i=1)
	std stores even reg in MS half, odd in LS (ignores dreg LSB?)

stba	op3=11/010101*	stba	rd, [address] asi (syn: stuba, stsba)
stha	op3=11/010110*	stha	rd, [address] asi (syn: stuha, stsha)
sta	op3=11/010100*	sta	rd, [address] asi
stda	op3=11/010111*	stda	rd, [address] asi
	store into rs1+rs2 (i=0) or take illegal instruction trap (i=1)
	std stores even reg in MS half, odd in LS (ignores dreg LSB?)

stf	op3=11/100100	st	fd, [address]
stdf	op3=11/100111	std	fd, [address]
stfsr	op3=11/100101	st	%fsr, [address]
stdfq	op3=11/100110*	std	%fq, [address]
	store into rs1+rs2 (i=0) or rs1+simm13 (i=1)
	[stdf] stores even f reg in MS half, odd in LS (ignores dreg LSB?)
	[stdfq] stores addr in MS half, instr in LS

stc	op3=11/110100	st	cd, [address]
stdc	op3=11/110111	std	cd, [address]
stcsr	op3=11/110101	st	%csr, [address]
stdcq	op3=11/110110*	std	%cq, [address]
	store into rs1+rs2 (i=0) or rs1+simm13 (i=1)
	[stdc] stores even c reg in MS half, odd in LS (ignores dreg LSB?)
	[stdcq] stores addr in MS half, instr in LS

ldstub	op3=11/001101	ldstub	[address], rd
	load/store rs1+rs2 (i=0) or rs1+simm13 (i=1)

ldstuba	op3=11/011101*	ldstuba	[address] asi, rd
	load/store rs1+rs2 (i=0) or take illegal instruction trap (i=1)

swap	op3=11/001111	swap	[address], rd
	swap rd with rs1+rs2 (i=0) or rs1+simm13 (i=1)

swapa	op3=11/011111*	swapa	[address] asi, rd
	swap rd with rs1+rs2 (i=0) or take illegal instruction trap (i=1)

add	op3=10/000000	add	rs1, reg/imm, rd
addcc	op3=10/010000	addcc	rs1, reg/imm, rd
addx	op3=10/001000	addx	rs1, reg/imm, rd
addxcc	op3=10/011000	addxcc	rs1, reg/imm, rd
taddcc	op3=10/100000	taddcc	rs1, reg/imm, rd
taddcctv op3=10/100010	taddcctv rs1, reg/imm, rd
sub	op3=10/000100	sub	rs1, reg/imm, rd
subcc	op3=10/010100	subcc	rs1, reg/imm, rd
subx	op3=10/001100	subx	rs1, reg/imm, rd
subxcc	op3=10/011100	subxcc	rs1, reg/imm, rd
tsubcc	op3=10/100001	tsubcc	rs1, reg/imm, rd
tsubcctv op3=10/100011	tsubcctv rs1, reg/imm, rd
mulscc	op3=10/100100	mulscc	rs1, reg/imm, rd
and	op3=10/000001	and	rs1, reg/imm, rd
andcc	op3=10/010001	andcc	rs1, reg/imm, rd
andn	op3=10/000101	andn	rs1, reg/imm, rd
andncc	op3=10/010101	andncc	rs1, reg/imm, rd
or	op3=10/000010	or	rs1, reg/imm, rd
orcc	op3=10/010010	orcc	rs1, reg/imm, rd
orn	op3=10/000110	orn	rs1, reg/imm, rd
orncc	op3=10/010110	orncc	rs1, reg/imm, rd
xor	op3=10/000011	xor	rs1, reg/imm, rd
xorcc	op3=10/010011	xorcc	rs1, reg/imm, rd
xnor	op3=10/000111	xnor	rs1, reg/imm, rd
xnorcc	op3=10/010111	xnorcc	rs1, reg/imm, rd
	asi ignored if i=0

sll	op3=10/100101	sll	rs1, reg/imm, rd
srl	op3=10/100110	srl	rs1, reg/imm, rd
sra	op3=10/100111	sra	rs1, reg/imm, rd
	asi ignored if i=0
	shift count is low 5 bits of immediate data if i=1 (high 8 ignored)

sethi	op2=100		sethi	const22, rd
			sethi	%hi(xxx), rd

save	op3=10/111100	save	rs1, reg/imm, rd
restore	op3=10/111101	restore	rs1, reg/imm, rd
	asi ignored if i=0
	like add, except rs1/rs2 fetched from old window, rd from new

bn	op2=010 cond=0000	bn	label
be	op2=010 cond=0001	be	label (syn: bz)
ble	op2=010 cond=0010	ble	label
bl	op2=010 cond=0011	bl	label
bleu	op2=010 cond=0100	bleu	label
bcs	op2=010 cond=0101	bcs	label (syn: blu)
bneg	op2=010 cond=0110	bneg	label
bvs	op2=010 cond=0111	bvs	label
ba	op2=010 cond=1000	ba	label
bne	op2=010 cond=1001	bne	label (syn: bnz)
bg	op2=010 cond=1010	bg	label
bge	op2=010 cond=1011	bge	label
bgu	op2=010 cond=1100	bgu	label
bcc	op2=010 cond=1101	bcc	label (syn: bgeu)
bpos	op2=010 cond=1110	bpos	label
bvc	op2=010 cond=1111	bvc	label
	append ,a to set annul bit

fbn	op2=110 cond=0000	fbn	label
fbne	op2=110 cond=0001	fbne	label (syn: fbnz)
fblg	op2=110 cond=0010	fblg	label
fbul	op2=110 cond=0011	fbul	label
fbl	op2=110 cond=0100	fbl	label
fbug	op2=110 cond=0101	fbug	label
fbg	op2=110 cond=0110	fbg	label
fbu	op2=110 cond=0111	fbu	label
fba	op2=110 cond=1000	fba	label
fbe	op2=110 cond=1001	fbe	label (syn: fbz)
fbue	op2=110 cond=1010	fbue	label
fbge	op2=110 cond=1011	fbge	label
fbuge	op2=110 cond=1100	fbuge	label
fble	op2=110 cond=1101	fble	label
fbule	op2=110 cond=1110	fbule	label
fbo	op2=110 cond=1111	fbo	label
	append ,a to set annul bit

cbn	op2=111 cond=0000	cbn	label
cb123	op2=111 cond=0001	cb123	label
cb12	op2=111 cond=0010	cb12	label
cb13	op2=111 cond=0011	cb13	label
cb1	op2=111 cond=0100	cb1	label
cb23	op2=111 cond=0101	cb23	label
cb2	op2=111 cond=0110	cb2	label
cb3	op2=111 cond=0111	cb3	label
cba	op2=111 cond=1000	cba	label
cb0	op2=111 cond=1001	cb0	label
cb03	op2=111 cond=1010	cb03	label
cb02	op2=111 cond=1011	cb02	label
cb023	op2=111 cond=1100	cb023	label
cb01	op2=111 cond=1101	cb01	label
cb013	op2=111 cond=1110	cb013	label
cb012	op2=111 cond=1111	cb012	label
	append ,a to set annul bit

call	opc=01		call	label
	%o7 (r15) gets addr of call, then pc += displ << 2

jmpl	op3=10/111000	jmpl	address, rd
	asi bits ignored if i=0
	jump to rs1+rs2 (i=0) or rs1+simm13 (i=1); rd gets addr of jmpl

rett	op3=10/111001*	rett	address
	dreg bits ignored
	asi bits ignored if i=0
	causes delayed transfer to rs1+rs2 (i=0) or rs1+simm13 (i=1)

ta	op3=10/111010 dreg=x1000	ta	label
tn	op3=10/111010 dreg=x0000	tn	label
tne	op3=10/111010 dreg=x1001	tne	label (syn: tnz)
te	op3=10/111010 dreg=x0001	te	label (syn: tz)
tg	op3=10/111010 dreg=x1010	tg	label
tle	op3=10/111010 dreg=x0010	tle	label
tge	op3=10/111010 dreg=x1011	tge	label
tl	op3=10/111010 dreg=x0011	tl	label
tgu	op3=10/111010 dreg=x1100	tgu	label
tleu	op3=10/111010 dreg=x0100	tleu	label
tcc	op3=10/111010 dreg=x1101	tcc	label (syn: tgeu)
tcs	op3=10/111010 dreg=x0101	tcs	label (syn: tlu)
tpos	op3=10/111010 dreg=x1110	tpos	label
tneg	op3=10/111010 dreg=x0110	tneg	label
tvc	op3=10/111010 dreg=x1111	tvc	label
tvs	op3=10/111010 dreg=x0111	tvs	label
	high bit of dreg ignored
	asi bits ignored if i=0
	trap code, if trap taken, is low 7 bits of
		rs1+rs2 (i=0) or rs1+simm13 (i=1)

rdy	op3=10/101000	rd	%y, rd
rdpsr	op3=10/101001*	rd	%psr, rd
rdwim	op3=10/101010*	rd	%wim, rd
rdtbr	op3=10/101011*	rd	%tbr, rd
	sreg1/i/asi/immediate/opf/sreg2 bits ignored

wry	op3=10/110000	wr	rs1, reg/imm, %y
wrpsr	op3=10/110001*	wr	rs1, reg/imm, %psr
wrwim	op3=10/110010*	wr	rs1, reg/imm, %wim
wrtbr	op3=10/110011*	wr	rs1, reg/imm, %tbr
	dreg bits ignored
	asi bits ignored if i=0
	delayed-write: after wrpsr, need three-instruction delay before
	using (even implicitly) any changed field; after wrwim, need
	three-instruction delay before doing save, restore, or rett; after
	wry, need three-instruction delay before mulscc or rdy; after any,
	reads of that register in the next three instructions produce
	unpredictable values; but if one of next three instrs traps, trap
	handler will see new value.

unimp	op2=000		unimp	const22
	dreg/const22 bits ignored
	causes illegal instruction trap

iflush	op3=10/111011	iflush	address
	flushes internal icache, if any, for rs1+rs2 (i=0) or rs1+simm13 (i=1)

fpop1	op3=10/110100
fpop2	op3=10/110101

fitos	opf=0/011000100	fitos	fs2, fd
fitod	opf=0/011001000	fitod	fs2, fd
fitox	opf=0/011001100	fitox	fs2, fd
fstoir	opf=0/011000001	fstoir	fs2, fd
fdtoir	opf=0/011000010	fdtoir	fs2, fd
fxtoir	opf=0/011000011	fxtoir	fs2, fd
fstoi	opf=0/011010001	fstoi	fs2, fd
fdtoi	opf=0/011010010	fdtoi	fs2, fd
fxtoi	opf=0/011010011	fxtoi	fs2, fd
fstod	opf=0/011001001	fstod	fs2, fd
fstox	opf=0/011001101	fstox	fs2, fd
fdtos	opf=0/011000110	fdtos	fs2, fd
fdtox	opf=0/011001110	fdtox	fs2, fd
fxtos	opf=0/011000111	fxtos	fs2, fd
fxtod	opf=0/011001011	fxtod	fs2, fd
fmovs	opf=0/000000001	fmovs	fs2, fd
fnegs	opf=0/000000101	fnegs	fs2, fd
fabss	opf=0/000001001	fabss	fs2, fd
fsqrts	opf=0/000101001	fsqrts	fs2, fd
fsqrtd	opf=0/000101010	fsqrtd	fs2, fd
fsqrtx	opf=0/000101011	fsqrtx	fs2, fd
	sreg1 bits ignored

fmuls	opf=0/001001001	fmuls	fs1, fs2, fd
fmuld	opf=0/001001010	fmuld	fs1, fs2, fd
fmulx	opf=0/001001011	fmulx	fs1, fs2, fd
fdivs	opf=0/001001101	fdivs	fs1, fs2, fd
fdivd	opf=0/001001110	fdivd	fs1, fs2, fd
fdivx	opf=0/001001111	fdivx	fs1, fs2, fd

fcmps	opf=1/001010001	fcmps	fs1, fs2
fcmpd	opf=1/001010010	fcmpd	fs1, fs2
fcmpx	opf=1/001010011	fcmpx	fs1, fs2
fcmpes	opf=1/001010101	fcmpes	fs1, fs2
fcmped	opf=1/001010110	fcmped	fs1, fs2
fcmpex	opf=1/001010111	fcmpex	fs1, fs2
	dreg bits ignored
	must execute non-fp instruction between fcmp* and following fb*

cpop1	op3=10/110110
cpop2	op3=10/110111