"32-bit" means if argument registers don't have bits N..31 all identical, result is undefined. "64-bit" means operation exists only on 64-bit processors and is 64 bits. "full-width" means full register width participates in operation. "branch" means sign-extended word offset (ie shifted left two bits) is added to address of delay slot to give new pc value after delay slot instruction executes "jump" means address replaces bits 27..2 of address of delay slot to give new pc value after delay slot instruction executes. "retaddr" means the address just past the delay slot. "goto" means replace pc with the specified value after the delay slot. "annul" means don't execute instruction in delay slot "half" is two-byte; "word" is four-byte; "double" is eight-byte. MFLO and MFHI must not be followed, in either of the succeeding two instructions, by anything that modifies them, or the value read is undefined. Divide/multiply instructions that modify HI/LO must have at least one value read with MFHI or MFLO before MTHI/MTLO is executed, or the HI/LO register contents go undefined. 000000 sssss ttttt ddddd 00000 100000 add rd, rs, rt rd = rs + rt; 32-bit, trap on signed overflow 001000 sssss ttttt iiiiiiiiiiiiiiii addi rt, rs, immediate rt = rs + sext(immediate); 32-bit, trap on signed overflow 001001 sssss ttttt iiiiiiiiiiiiiiii addiu rt, rs, immediate rt = rs + sext(immediate); 32-bit, no overflow trap 000000 sssss ttttt ddddd 00000 100001 addu rd, rs, rt rd = rs + rt; 32-bit, no overflow trap 000000 sssss ttttt ddddd 00000 100100 and rd, rs, rt rd = rs & rt; full-width 001100 sssss ttttt iiiiiiiiiiiiiiii andi rt, rs, immediate rt = rs & zext(immediate); full-width 000100 sssss ttttt oooooooooooooooo beq rs, rt, offset if (rs == rt) branch 010100 sssss ttttt oooooooooooooooo II beql rs, rt, offset if (rs == rt) branch else annul 000001 sssss 00001 oooooooooooooooo bgez rs, offset if (rs >=s 0) branch 000001 sssss 10001 oooooooooooooooo bgezal rs, offset $31=retaddr; if (rs >=s 0) branch 000001 sssss 10011 oooooooooooooooo II bgezall rs, offset $31=retaddr; if (rs >=s 0) branch else annul 000001 sssss 00011 oooooooooooooooo II bgezl rs, offset if (rs >=s 0) branch else annul 000111 sssss 00000 oooooooooooooooo bgtz rs, offset if (rs >s 0) branch 010111 sssss 00000 oooooooooooooooo II bgtzl rs, offset if (rs >s 0) branch else annul 000110 sssss 00000 oooooooooooooooo blez rs, offset if (rs <=s 0) branch 010110 sssss 00000 oooooooooooooooo II blezl rs, offset if (rs <=s 0) branch else annul 000001 sssss 00000 oooooooooooooooo bltz rs, offset if (rs >a sa; 64-bit 000000 00000 ttttt ddddd aaaaa 111111 III dsra32 rd, rt, sa rd = rt >>a (32+sa); 64-bit 000000 sssss ttttt ddddd 00000 010111 III dsrav rd, rt, rs rd = rt >>a low6(rs); 64-bit 000000 00000 ttttt ddddd aaaaa 111010 III dsrl rd, rt, sa rd = rt >>l sa; 64-bit 000000 00000 ttttt ddddd aaaaa 111110 III dsrl32 rd, rt, sa rd = rt >>l (32+sa); 64-bit 000000 sssss ttttt ddddd 00000 010110 III dsrlv rd, rt, rs rd = rt >>l low6(rs); 64-bit 000000 sssss ttttt ddddd 00000 101110 III dsub rd, rs, rt rd = rs - rt; 64-bit, trap on signed overflow 000000 sssss ttttt ddddd 00000 101111 III dsubu rd, rs, rt rd = rs - rt; 64-bit, no overflow trap 000010 aaaaaaaaaaaaaaaaaaaaaaaaaa j target jump 000011 aaaaaaaaaaaaaaaaaaaaaaaaaa jal target $31=retaddr; jump 000000 sssss 00000 ddddd 00000 001001 jalr rs (rd=$31 implied) jalr rd, rs rd=retaddr; goto rs 000000 sssss 000000000000000 001000 jr rs goto rs 100000 bbbbb ttttt oooooooooooooooo lb rt, offset(rb) rt = sext(memory.byte[rb+offset]) 100100 bbbbb ttttt oooooooooooooooo lbu rt, offset(rb) rt = zext(memory.byte[rb+offset]) 110111 bbbbb ttttt oooooooooooooooo III ld rt, offset(rb) rt = memory.double[rb+offset] all: rb+offset must be aligned; MIPS IV: offset must be aligned 1101zz bbbbb ttttt oooooooooooooooo II ldc rt, offset(rb) loads coprocessor #zz register rt with memory.double[rb+offset] all: rb+offset must be aligned; MIPS IV: offset must be aligned not available for zz=00 or zz=11 011010 bbbbb ttttt oooooooooooooooo III ldl rt, offset(rb) load most-significant part of unaligned double from memory 011011 bbbbb ttttt oooooooooooooooo III ldr rt, offset(rb) load least-significant part of unaligned double from memory 100001 bbbbb ttttt oooooooooooooooo lh rt, offset(rb) rt = sext(memory.half[rb+offset]) all: rb+offset must be aligned; MIPS IV: offset must be aligned 100101 bbbbb ttttt oooooooooooooooo lhu rt, offset(rb) rt = zext(memory.half[rb+offset]) all: rb+offset must be aligned; MIPS IV: offset must be aligned 110000 bbbbb ttttt oooooooooooooooo II ll rt, offset(rb) rt = sext(memory.word[rb+offset]); also start RMW sequence all: rb+offset must be aligned; MIPS IV: offset must be aligned 110100 bbbbb ttttt oooooooooooooooo III lld rt, offset(rb) rt = memory.double[rb+offset]; also start RMW sequence all: rb+offset must be aligned; MIPS IV: offset must be aligned 001111 00000 ttttt iiiiiiiiiiiiiiii lui rt, immediate rt = sext(immediate<<16) 100011 bbbbb ttttt oooooooooooooooo lw rt, offset(rb) rt = sext(memory.word[rb+offset]) all: rb+offset must be aligned; MIPS IV: offset must be aligned 1100zz bbbbb ttttt oooooooooooooooo lwc rt, offset(rb) loads coprocessor #zz register rt with memory.word[rb+offset] all: rb+offset must be aligned; MIPS IV: offset must be aligned not available for zz=00 or zz=11 100010 bbbbb ttttt oooooooooooooooo lwl rt, offset(rb) load most-significant part of unaligned word from memory 100110 bbbbb ttttt oooooooooooooooo lwr rt, offset(rb) load least-significant part of unaligned word from memory 100111 bbbbb ttttt oooooooooooooooo III lwu rt, offset(rb) rt = zext(memory.word[rb+offset]) all: rb+offset must be aligned; MIPS IV: offset must be aligned 000000 0000000000 ddddd 00000 010000 mfhi rd rd = HI 000000 0000000000 ddddd 00000 010010 mflo rd rd = HI 000000 sssss ttttt ddddd 00000 001011 IV movn rd, rs, rt if (rt != 0) rd = rs 000000 sssss ttttt ddddd 00000 001010 IV movz rd, rs, rt if (rt == 0) rd = rs 000000 sssss 000000000000000 010001 mthi rs HI = rs 000000 sssss 000000000000000 010011 mtlo rs LO = rs 000000 sssss ttttt 0000000000 011000 mult rs, rt (HI,LO) = rs *s rt; 32-bit 000000 sssss ttttt 0000000000 011001 multu rs, rt (HI,LO) = rs *u rt; 32-bit 000000 sssss ttttt ddddd 00000 100111 nor rd, rs, rt rd = ~ (rs | rt); full-width 000000 sssss ttttt ddddd 00000 100101 or rd, rs, rt rd = rs | rt; full-width 001101 sssss ttttt iiiiiiiiiiiiiiii ori rt, rs, immediate rt = rs | zext(immediate) 110011 bbbbb hhhhh oooooooooooooooo pref hint, offset(rb) prefetch hint for memory[rb+offset]; never causes exception hint values: 0 load - expect data to be read, not written 1 store - expect data to be written 4 load-stream - read, but not repeatedly 5 store-stream - write, but not repeatedly 6 load-retain - read repeatedly 7 store-retain - write repeatedly other not defined 101000 bbbbb ttttt oooooooooooooooo sb rt, offset(rb) memory.byte[rb+offset] = rt 111000 bbbbb ttttt oooooooooooooooo II sc rt, offset(rb) if (RMW sequence is atomic) memory.word[rb+offset] = rt rt = 1 else rt = 0 all: rb+offset must be aligned; MIPS IV: offset must be aligned 111100 bbbbb ttttt oooooooooooooooo III scd rt, offset(rb) if (RMW sequence is atomic) memory.double[rb+offset] = rt rt = 1 else rt = 0 all: rb+offset must be aligned; MIPS IV: offset must be aligned 111111 bbbbb ttttt oooooooooooooooo III sd rt, offset(rb) memory.double[rb+offset] = rt all: rb+offset must be aligned; MIPS IV: offset must be aligned 1111zz bbbbb ttttt oooooooooooooooo II sdc rt, offset(rb) stores comprocessor #zz register rt into memory.double[rb+offset] all: rb+offset must be aligned; MIPS IV: offset must be aligned not available for zz=00 or zz=11 101100 bbbbb ttttt oooooooooooooooo III sdl rt, offset(rb) stores most-significant part of unaligned double into memory 101101 bbbbb ttttt oooooooooooooooo III sdr rt, offset(rb) stores least-significant part of unaligned double into memory 101001 bbbbb ttttt oooooooooooooooo sh rt, offset(rb) memory.half[rb+offset] = rt all: rb+offset must be aligned; MIPS IV: offset must be aligned 000000 00000 ttttt ddddd aaaaa 000000 sll rd, rt, sa rd = sext(low32(rt)<>a sa; 32-bit 000000 sssss ttttt ddddd 00000 000111 srav rd, rt, rs rd = rt >>a low5(rs); 32-bit 000000 00000 ttttt ddddd aaaaa 000010 srl rd, rt, sa rd = rt >>l sa; 32-bit 000000 sssss ttttt ddddd 00000 000110 srlv rd, rt, rs rd = rt >>l low5(rs); 32-bit 000000 sssss ttttt ddddd 00000 100010 sub rd, rs, rt rd = rs - rt; 32-bit, trap on signed overflow 000000 sssss ttttt ddddd 00000 100011 subu rd, rs, rt rd = rs - rt; 32-bit, no overflow trap 101011 bbbbb ttttt oooooooooooooooo sw rt, offset(rb) memory.word[rb+offset] = rt all: rb+offset must be aligned; MIPS IV: offset must be aligned 1110zz bbbbb ttttt oooooooooooooooo swc rt, offset(rb) stores coprocessor #zz register rt into memory.word[rb+offset] all: rb+offset must be aligned; MIPS IV: offset must be aligned not available for zz=00 or zz=11 101010 bbbbb ttttt oooooooooooooooo swl rt, offset(rb) stores most-significant part of unaligned word into memory 101110 bbbbb ttttt oooooooooooooooo swr rt, offset(rb) stores least-significant part of unaligned word into memory 000000 000000000000000 sssss 001111 II sync (sss=0 implied) force ordering of memory accesses wrt shared memory 000000 cccccccccccccccccccc 001100 syscall produce syscall exception; ccc bits available to handler 000000 sssss ttttt cccccccccc 110100 II teq rs, rt if (rs == rt) trap 000001 sssss 01100 iiiiiiiiiiiiiiii II teqi rs, immediate if (rs == sext(immediate)) trap 000000 sssss ttttt cccccccccc 110000 II tge rs, rt if (rs >=s rt) trap 000001 sssss 01000 iiiiiiiiiiiiiiii II tgei rs, immediate if (rs >=s sext(immediate)) trap 000001 sssss 01001 iiiiiiiiiiiiiiii II tgeiu rs, immediate if (rs >=u sext(immediate)) trap 000000 sssss ttttt cccccccccc 110001 II tgeu rs, rt if (rs >=u rt) trap 000000 sssss ttttt cccccccccc 110010 II tlt rs, rt if (rs .[sd] fs, ft c.

.[sd] cc, fs, ft IV if (p3 && operand is QNaN) generate exception set fcc[cc] to (p2 && (fs condition 0000 f always false 0001 un unordered 0010 eq equal 0011 ueq unordered or equal 0100 olt ordered and less than 0101 ult unordered or less than 0110 ole ordered and less or equal 0111 ule unordered or less or equal 1000 sf signaling false 1001 ngle not greater, less, nor equal 1010 seq signaling equal 1011 ngl not greater nor less 1100 lt less than 1101 nge not greater nor equal 1110 le less or equal 1111 ngt not greater 010001 fffff 00000 sssss ddddd 001010 III ceil.l.[sd] fd, fs fd = fs, rounded towards +infty and converted to format l 010001 fffff 00000 sssss ddddd 001110 II ceil.w.[sd] fd, fs fd = fs, rounded towards +infty and converted to format w 010001 00010 ttttt sssss 00000000000 cfc1 rt, fs rt = sext(fp control register fs) 010001 00110 ttttt sssss 00000000000 ctc1 rt, fs fp control register fs = rt 010001 fffff 00000 sssss ddddd 100001 cvt.d.[swl] fd, fs fd = fs, converted to format d 010001 fffff 00000 sssss ddddd 100101 III cvt.l.[sd] fd, fs fd = fs, converted to format l 010001 fffff 00000 sssss ddddd 100000 cvt.s.[dwl] fd, fs fd = fs, converted to format s 010001 fffff 00000 sssss ddddd 100100 cvt.w.[sd] fd, fs fd = fs, converted to format w 010001 fffff ttttt sssss ddddd 000011 div.[sd] fd, fs, ft fd = fs / ft 010001 00001 ttttt sssss 00000000000 III dmfc1 rt, fs rt = fs, doubleword bit copy 010001 00101 ttttt sssss 00000000000 III dmtc1 rt, fs fs = rt, doubleword bit copy 010001 fffff 00000 sssss ddddd 001011 III floor.l.[sd] fd, fs fd = fs, rounded towards -infty and converted to format l 010001 fffff 00000 sssss ddddd 001111 II floor.w.[sd] fd, fs fd = fs, rounded towards -infty and converted to format w 110101 bbbbb ttttt oooooooooooooooo II ldc1 ft, offset(rb) ft = memory.double[rb+offset] all: rb+offset must be aligned; MIPS IV: offset must be aligned 010011 bbbbb xxxxx 00000 ddddd 000001 IV ldxc1 fd, rx(rb) fd = memory.double[rb+rx] rb+rx<63-62> must equal rb<63-62>; rb and rx must be aligned 110001 bbbbb ttttt oooooooooooooooo lwc1 ft, offset(rb) ft = memory.word[rb+offset] all: rb+offset must be aligned; MIPS IV: offset must be aligned 010011 bbbbb xxxxx 00000 ddddd 000000 IV lwxc1 fd, rx(rb) fd = memory.word[rb+rx] rb+rx<63-62> must equal rb<63-62>; rb and rx must be aligned 010011 rrrrr ttttt sssss ddddd 100 fff IV madd.s fd, fr, fs, ft madd.d fd, fr, fs, ft fd = (fs * ft) + fr 010001 00000 ttttt sssss 00000000000 mfc1 rt, fs rt = fs 010001 fffff 00000 sssss ddddd 000110 mov.[sd] fd, fs fd = fs 000000 sssss ccc 0 0 ddddd 00000 000001 IV movf rd, rs, cc if (cc == 0) rd = rs 010001 fffff ccc 0 0 sssss ddddd 010001 IV movf.[sd] fd, fs, cc if (cc == 0) fd = fs 010001 fffff ttttt sssss ddddd 010011 IV movn.[sd] fd, fs, rt if (rt != 0) fd = fs 000000 sssss ccc 0 1 ddddd 00000 000001 IV movt rd, rs, cc if (cc == 1) rd = rs 010001 fffff ccc 0 1 sssss ddddd 010001 IV movt.[sd] fd, fs, cc if (cc == 1) fd = fs 010001 fffff ttttt sssss ddddd 010010 IV movz.[sd] fd, fs, rt if (rt == 0) fd = fs 010011 rrrrr ttttt sssss ddddd 101 fff IV msub.s fd, fr, fs, ft msub.d fd, fr, fs, ft fd = (fs * ft) - fr 010001 00100 ttttt sssss 00000000000 mtc1 rt, fs fs = rt 010001 fffff ttttt sssss ddddd 000010 mul.[sd] fd, fs, ft fd = fs * ft 010001 fffff 00000 sssss ddddd 000111 neg.[sd] fd, fs fd = - fs 010011 rrrrr ttttt sssss ddddd 110 fff IV nmadd.s fd, fr, fs, ft nmadd.d fd, fr, fs, ft fd = - ((fs * ft) + fr) 010011 rrrrr ttttt sssss ddddd 111 fff IV nmsub.s fd, fr, fs, ft nmsub.d fd, fr, fs, ft fd = - ((fs * ft) - fr) 010011 bbbbb xxxxx hhhhh 00000 001111 IV prefx hint, rx(rb) similar to pref, but address is rx+rb rb+rx<63-62> must equal rb<63-62>; rb and rx must be aligned 010001 fffff 00000 sssss ddddd 010101 IV recip.[sd] fd, fs fd = 1 / fs 010001 fffff 00000 sssss ddddd 001000 III round.l.[sd] fd, fs fd = fs, rounded to nearest and converted to format l 010001 fffff 00000 sssss ddddd 001100 II round.w.[sd] fd, fs fd = fs, rounded to nearest and converted to format w 010001 fffff 00000 sssss ddddd 010110 IV rsqrt.[sd] fd, fs fd = 1 / sqrt(fs) 111101 bbbbb ttttt oooooooooooooooo II sdc1 fd, offset(rb) memory.double[rb+offset] = fd all: rb+offset must be aligned; MIPS IV: offset must be aligned 010011 bbbbb xxxxx sssss 00000 001001 IV sdxc1 fs, rx(rb) memory.double[rx+rb] = fs rb+rx<63-62> must equal rb<63-62>; rb and rx must be aligned 010001 fffff 00000 sssss ddddd 000100 II sqrt.[sd] fd, fs fd = sqrt(fs) 010001 fffff ttttt sssss ddddd 000001 sub.[sd] fd, fs, ft fd = fs - ft 111001 bbbbb ttttt oooooooooooooooo swc1 ft, offset(rb) memory.word[rb+offset] = ft all: rb+offset must be aligned; MIPS IV: offset must be aligned 010011 bbbbb xxxxx sssss 00000 001000 IV swxc1 fs, rx(rb) memory.word[rb+rx] = fs rb+rx<63-62> must equal rb<63-62>; rb and rx must be aligned 010001 fffff 00000 sssss ddddd 001001 III trunc.l.[sd] fd, fs fd = fs, rounded towards zero and converted to format l 010001 fffff 00000 sssss ddddd 001101 II trunc.w.[sd] fd, fs fd = fs, rounded towards zero and converted to format l