/* This file is in the public domain. */

#include "machine-m68k.h"

/*
numbers can be either single-digit hex 0-9A-F (note: lowercase not allowed)
or multi-digit hex in parens.  Bits are numbered from LSB to MSB within each
word, with each word numbered 16 (0x10) higher than the preceding word.
%dX - data register, number in (opcode>>X)&7
%aX - address register, number in (opcode>>X)&7
%rX - register, %aX if (opcode>>X)&8, %dX else
%sX - size letter, "bwl?"[(opcode>>X)&3] (? is an error)
	other things that specify sizes can use S to mean "size of last %s";
	if X is v, format is %svABCDX, and letter is
	"ABCD"[(opcode>>X)&3].  if X is V, format is %sVABX, and letter is
	"AB"[(opcode>>X)&1].  if X is f, format is %sfX, and letter is
	"lsxpwdb?"[(opcode>>X)&7], for 6888x instructions.
%SX - like %sX but doesn't print anything
%GWXYZ - effective-address operand
	W specifies size as for %sX, or is letter b/w/l
	X is allowed modes code (below)
	Y is where m is: (opcode>>Y)&7
	Z is where r is: (opcode>>Z)&7
	mode 1 = all modes except address register direct if byte
	mode 2 = data modes except:
			data register direct if double, extended or packed float
	mode 3 = alterable memory modes
	mode 4 = data alterable modes except:
			data register direct if double, extended or packed float
	mode 5 = alterable modes, except address register direct if byte
	mode 6 = data register direct or control
	mode 7 = control modes
	mode 8 = control alterable modes
	mode 9 = data register direct or alterable control
	mode a = data modes except immediate
	mode b = postincrement or control (immediate mode disallowed)
	mode c = predecrement or control alterable
%gX - like %GsX30
%iFX - immediate data; X is size as for %g, F is format to print it with
	b - binary
	d - decimal
	u - unsigned decimal
	x - hex
	q - like u except that all-bits-0 is mapped to all-bits-1 plus 1
	s - like x with sr bits listed
	g - heuristic for base, same as for immediate mode general operands
	m+ - movem mask, a7a6a5..d2d1d0
	m- - movem mask, d0d1d2...a5a6a7
	M+ - fmovem mask, fp7...fp0
	M- - fmovem mask, fp0...fp7
	S - use default format for size
	immediate data follows immediately after all opcode words
%CX - movec control register argument: (opcode>>X)&07777
%cX - branch condition code (opcode>>X)&017:
	0000 - t	0100 - cc	1000 - vc	1100 - ge
	0001 - f	0101 - cs	1001 - vs	1101 - lt
	0010 - hi	0110 - ne	1010 - pl	1110 - gt
	0011 - ls	0111 - eq	1011 - mi	1111 - le
	if X has * before it, 0000 and 0001 are errors rather than t/f
	condition code is normally two characters - t and f are followed by a space
	if X has ! before it, space is not added to t and f
	if X has p before it, nothing is output except, for t and f, a space
%FcX - floating-point branch condition code (opcode>>X)&077:
	000000 - t	010000 - sf	100000 - ?40	110000 - ?60
	000001 - eq	010001 - seq	100001 - ?41	110001 - ?61
	000010 - ogt	010010 - gt	100010 - ?42	110010 - ?62
	000011 - oge	010011 - ge	100011 - ?43	110011 - ?63
	000100 - olt	010100 - lt	100100 - ?44	110100 - ?64
	000101 - ole	010101 - le	100101 - ?45	110101 - ?65
	000110 - ogl	010110 - gl	100110 - ?46	110110 - ?66
	000111 - or	010111 - gle	100111 - ?47	110111 - ?67
	001000 - un	011000 - ngle	101000 - ?50	111000 - ?70
	001001 - ueq	011001 - ngl	101001 - ?51	111001 - ?71
	001010 - ugt	011010 - nle	101010 - ?52	111010 - ?72
	001011 - uge	011011 - nlt	101011 - ?53	111011 - ?73
	001100 - ult	011100 - nge	101100 - ?54	111100 - ?74
	001101 - ule	011101 - ngt	101101 - ?55	111101 - ?75
	001110 - ne	011110 - sne	101110 - ?56	111110 - ?76
	001111 - f	011111 - st	101111 - ?57	111111 - ?77
	By default, this is padded with spaces to 4 characters.  If
	%F!c is used, no padding is added; if %F+c is used, only the
	padding is produced.  (If both are used, nothing is output.)
%FrX - ROM constant name (opcode>>X)&0177:
	0000000 - pi
	0001011 - log10(2)
	0001100 - e
	0001101 - log2(e)
	0001110 - log10(e)
	0001111 - zero
	0110000 - ln(2)
	0110001 - ln(10)
	0110010 - 1
	0110011 - 10
	0110100 - 10^2
	0110101 - 10^4
	0110110 - 10^8
	0110111 - 10^16
	0111000 - 10^32
	0111001 - 10^64
	0111010 - 10^128
	0111011 - 10^256
	0111100 - 10^512
	0111101 - 10^1024
	0111110 - 10^2048
	0111111 - 10^4096
	other - unknown
%t - branch target, displacement in opcode&0xff
	if this value is zero, use 16-bit displacement in next word
	if this value is 0xff, use 32-bit displacement in next two words
%TX - branch target, displacement is in next word (X is w) or long (X is l).
%vFXY - general value, low Y bits of (opcode>>X) according to format F
%BoX - bitfield offset, (opcode>>X)&077 describes offset
%BwX - bitfield width, (opcode>>X)&077 describes width
%?CWXYZ...%|...%. - conditional
	if low X bits of (opcode>>W) C low Y bits of (opcode>>Z),
	then do first ...
	else do second ...
	C can be <, =, or >
	W and Y can have optional + inserted before them to
	indicate sign-extension of that comparison operand
	also, if W (Y) is ! then operand is literally X (Z).
%X - fail immediately
*/

INSTR Machine_m68k_instrs[] = { { 1, { { 0170770, 0140400 } }, "abcd    %d0,%d9" },
				{ 1, { { 0170770, 0140410 } }, "abcd    %a0@-,%a9@-" },
				{ 1, { { 0170400, 0150000 } }, "add%s6    %g1,%d9" },
				{ 1, { { 0170400, 0150400 } }, "add%s6    %d9,%g3" },
				{ 1, { { 0170300, 0150300 } }, "add%sVwl8    %g1,%a9" }, /* adda */
				{ 1, { { 0177400, 0003000 } }, "add%s6    #%igS,%g4" }, /* addi */
				{ 1, { { 0170400, 0050000 } }, "addq%s6   #%vq93,%g5" },
				{ 1, { { 0170470, 0150400 } }, "addx%s6   %d0,%d9" },
				{ 1, { { 0170470, 0150410 } }, "addx%s6   %a0@-,%a9@-" },
				{ 1, { { 0170400, 0140000 } }, "and%s6    %g2,%d9" },
				{ 1, { { 0170400, 0140400 } }, "and%s6    %d9,%g3" },
				{ 1, { { 0177400, 0001000 } }, "and%s6    #%ixS,%g4" }, /* andi */
				{ 1, { { 0177777, 0001074 } }, "and     #%isb,ccr" }, /* andi */
				{ 1, { { 0177777, 0001174 } }, "and     #%isw,sr" }, /* andi */
				{ 1, { { 0170470, 0160000 } }, "asr%s6    #%vq93,%d0" },
				{ 1, { { 0170470, 0160040 } }, "asr%s6    %d9,%d0" },
				{ 1, { { 0170470, 0160400 } }, "asl%s6    #%vq93,%d0" },
				{ 1, { { 0170470, 0160440 } }, "asl%s6    %d9,%d0" },
				{ 1, { { 0177700, 0160300 } }, "asr     %Sw%g3" },
				{ 1, { { 0177700, 0160700 } }, "asl     %Sw%g3" },
				{ 1, { { 0170000, 0060000 } }, "b%c*8     %t" },
				{ 1, { { 0170700, 0000500 } }, "bchg    %Sb%d9,%g4" },
				{ 1, { { 0177700, 0004100 } }, "bchg    %Sb#%iuS,%g4" },
				{ 1, { { 0170700, 0000600 } }, "bclr    %Sb%d9,%g4" },
				{ 1, { { 0177700, 0004200 } }, "bclr    %Sb#%iuS,%g4" },
				{ 2, { { 0177700, 0165300 }, { 0170000, 0000000 } }, "bfchg   %Sb%g9{%Bo(16):%Bw(10)}" },
				{ 2, { { 0177700, 0166300 }, { 0170000, 0000000 } }, "bfclr   %Sb%g9{%Bo(16):%Bw(10)}" },
				{ 2, { { 0177700, 0165700 }, { 0100000, 0000000 } }, "bfexts  %Sb%g6{%Bo(16):%Bw(10)},%d(1C)" },
				{ 2, { { 0177700, 0164700 }, { 0100000, 0000000 } }, "bfextu  %Sb%g6{%Bo(16):%Bw(10)},%d(1C)" },
				{ 2, { { 0177700, 0166700 }, { 0100000, 0000000 } }, "bfffo   %Sb%g6{%Bo(16):%Bw(10)},%d(1C)" },
				{ 2, { { 0177700, 0167700 }, { 0100000, 0000000 } }, "bfins   %Sb%d(1C),%g9{%Bo(16):%Bw(10)}" },
				{ 2, { { 0177700, 0167300 }, { 0170000, 0000000 } }, "bfset   %Sb%g9{%Bo(16):%Bw(10)}" },
				{ 2, { { 0177700, 0164300 }, { 0170000, 0000000 } }, "bftst   %Sb%g6{%Bo(16):%Bw(10)}" },
				{ 1, { { 0177770, 0044110 } }, "bkpt    #%vu03" },
				{ 1, { { 0177400, 0060000 } }, "bra     %t" },
				{ 1, { { 0170700, 0000700 } }, "bset    %Sb%d9,%g4" },
				{ 1, { { 0177700, 0004300 } }, "bset    %Sb#%iuS,%g4" },
				{ 1, { { 0177400, 0060400 } }, "bsr     %t" },
				{ 1, { { 0170700, 0000400 } }, "btst    %Sb%d9,%g4" },
				{ 1, { { 0177700, 0004000 } }, "btst    %Sb#%iuS,%g4" },
				{ 2, { { 0177700, 0003300 }, { 0177400, 0000000 } }, "callm   #%vu(10)8,%Sb%g7" },
				{ 2, { { 0174300, 0004300 }, { 0177070, 0000000 } }, "cas%sv?bwl9    %d(10),%d(16),%g3" },
				{ 3, { { 0176377, 0006374 }, { 0007070, 0000000 }, { 0007070, 0000000 } }, "cas2%sVwl9   %d(10):%d(20),%d(16):%d(26),%r(1C)@,%r(2C)@" },
				{ 1, { { 0170500, 0040400 } }, "chk%sVlw7    %g2,%d9" },
				{ 2, { { 0174700, 0000300 }, { 0007777, 0004000 } }, "chk2%s9   %g7,%r(1C)" },
				{ 1, { { 0177400, 0041000 } }, "clr%s6    %g4" },
				{ 1, { { 0170400, 0130000 } }, "cmp%s6    %g1,%d9" },
				{ 1, { { 0170300, 0130300 } }, "cmp%sVwl8    %g1,%a9" }, /* cmpa */
				{ 1, { { 0177400, 0006000 } }, "cmp%s6    #%igS,%ga" }, /* cmpi */
				{ 1, { { 0170470, 0130410 } }, "cmp%s6    %a0@+,%a9@+" }, /* cmpm */
				{ 2, { { 0174700, 0000300 }, { 0007777, 0000000 } }, "cmp2%s9   %g7,%r(1C)" },
				{ 1, { { 0170370, 0050310 } }, "db%c8    %d0,%Tw" },
				{ 1, { { 0170700, 0100700 } }, "divs%sw   %g2,%d9" },
				{ 2, { { 0177700, 0046100 }, { 0105770, 0004000 } }, "divs%?=(1A)1!1q%|l%.%sl  %g2,%d(10)%?=(10)3(1C)3%|:%d(1C)%." },
				{ 1, { { 0170700, 0100300 } }, "divu%sw   %g2,%d9" },
				{ 2, { { 0177700, 0046100 }, { 0105770, 0000000 } }, "divu%?=(1A)1!1q%|l%.%sl  %g2,%d(10)%?=(10)3(1C)3%|:%d(1C)%." },
				{ 1, { { 0170400, 0130400 } }, "eor%s6    %d9,%g4" },
				{ 1, { { 0177400, 0005000 } }, "eor%s6    #%ixS,%g4" }, /* eori */
				{ 1, { { 0177777, 0005074 } }, "eor     #%isb,ccr" },
				{ 1, { { 0177777, 0005174 } }, "eor     #%isw,sr" },
				{ 1, { { 0170770, 0140500 } }, "exg     %d9,%d0" },
				{ 1, { { 0170770, 0140510 } }, "exg     %a9,%a0" },
				{ 1, { { 0170770, 0140610 } }, "exg     %d9,%a0" },
				{ 1, { { 0177770, 0044200 } }, "extbw   %d0" },
				{ 1, { { 0177770, 0044300 } }, "extwl   %d0" },
				{ 1, { { 0177770, 0044700 } }, "extbl   %d0" },
				{ 1, { { 0177777, 0045374 } }, "illegal" },
				{ 1, { { 0177700, 0047300 } }, "jmp     %Sb%g7" },
				{ 1, { { 0177700, 0047200 } }, "jsr     %Sb%g7" },
				{ 1, { { 0170700, 0040700 } }, "lea     %Sl%g7,%a9" },
				{ 1, { { 0177770, 0047120 } }, "linkw   %a0,#%idw" },
				{ 1, { { 0177770, 0044010 } }, "linkl   %a0,#%idl" },
				{ 1, { { 0170070, 0160010 } }, "ls%?=81!1l%|r%.%s6    #%vq93,%d0" },
				{ 1, { { 0170070, 0160050 } }, "ls%?=81!1l%|r%.%s6    %d9,%d0" },
				{ 1, { { 0177300, 0161300 } }, "ls%?=81!1l%|r%.     %Sb%g3" },
				{ 1, { { 0140000, 0000000 } }, "move%sv?blwC   %g1,%GS469" },
				{ 1, { { 0160700, 0020100 } }, "move%sVlwC   %g1,%a9" }, /* movea */
				{ 1, { { 0177700, 0041300 } }, "move    %Swccr,%g4" },
				{ 1, { { 0177777, 0042374 } }, "move    #%isb,ccr" },
				{ 1, { { 0177700, 0042300 } }, "move    %Sw%ga,ccr" },
				{ 1, { { 0177700, 0040300 } }, "move    %Swsr,%g4" },
				{ 1, { { 0177777, 0043374 } }, "move    #%isw,sr" },
				{ 1, { { 0177700, 0043300 } }, "move    %Sw%ga,sr" },
				{ 1, { { 0177770, 0047140 } }, "move    %a0,usp" },
				{ 1, { { 0177770, 0047150 } }, "move    usp,%a0" },
				{ 2, { { 0177777, 0047172 }, { 0000000, 0000000 } }, "movec   %C(10),%r(1C)" },
				{ 2, { { 0177777, 0047173 }, { 0000000, 0000000 } }, "movec   %r(1C),%C(10)" },
				{ 2, { { 0177670, 0044240 }, { 0000000, 0000000 } }, "movem%sVwl6  #%vm-(10)(10),%a0@-" },
				{ 2, { { 0177600, 0044200 }, { 0000000, 0000000 } }, "movem%sVwl6  #%vm+(10)(10),%g8" },
				{ 2, { { 0177670, 0046230 }, { 0000000, 0000000 } }, "movem%sVwl6  %a0@+,#%vm+(10)(10)" },
				{ 2, { { 0177600, 0046200 }, { 0000000, 0000000 } }, "movem%sVwl6  %g7,#%vm+(10)(10)" },
				{ 1, { { 0170670, 0000410 } }, "movep%sVwl6  %a0@(%igw),%d9" },
				{ 1, { { 0170670, 0000610 } }, "movep%sVwl6  %d9,%a0@(%igw)" },
				{ 1, { { 0170400, 0070000 } }, "moveq   #%vd08,%d9" },
				{ 2, { { 0177400, 0007000 }, { 0007777, 0000000 } }, "moves%s6  %g3,%r(1C)" },
				{ 2, { { 0177400, 0007000 }, { 0007777, 0004000 } }, "moves%s6  %r(1C),%g3" },
				{ 1, { { 0170700, 0140700 } }, "muls%sw   %g2,%d9" },
/* doc has a cut-&-paste error (pg 3-134), shows Dr and Dq but talks about Dh and Dl. */
/* the two data registers here may be interchanged, but I think not because this way */
/*  mulsl and mulul agree - and mulul doesn't have this error. */
				{ 2, { { 0177700, 0046000 }, { 0105770, 0004000 } }, "muls%sl   %g2,%?=(1A)1!1%d(10):%.%d(1C)" },
				{ 1, { { 0170700, 0140300 } }, "mulu%sw   %g2,%d9" },
				{ 2, { { 0177700, 0046000 }, { 0105770, 0000000 } }, "mulu%sl   %g2,%?=(1A)1!1%d(10):%.%d(1C)" },
				{ 1, { { 0177700, 0044000 } }, "nbcd    %Sb%g4" },
				{ 1, { { 0177400, 0042000 } }, "neg%s6    %g4" },
				{ 1, { { 0177400, 0040000 } }, "negx%s6   %g4" },
				{ 1, { { 0177777, 0047161 } }, "nop" },
				{ 1, { { 0177400, 0043000 } }, "not%s6    %g4" },
				{ 1, { { 0170400, 0100000 } }, "or%s6     %g2,%d9" },
				{ 1, { { 0170400, 0100400 } }, "or%s6     %d9,%g3" },
				{ 1, { { 0177400, 0000000 } }, "or%s6     #%ixS,%g4" }, /* ori */
				{ 1, { { 0177777, 0000074 } }, "or      #%isb,ccr" },
				{ 1, { { 0177777, 0000174 } }, "or      #%isw,sr" },
				{ 1, { { 0170770, 0100500 } }, "pack    %d0,%d9,#%ixw" },
				{ 1, { { 0170770, 0100510 } }, "pack    %a0@-,%a9@-,#%ixw" },
				{ 1, { { 0177700, 0044100 } }, "pea     %Sb%g7" },
				{ 1, { { 0177777, 0047160 } }, "reset" },
				{ 1, { { 0170070, 0160030 } }, "ro%?=81!1l%|r%.%s6    #%vq93,%d0" },
				{ 1, { { 0170070, 0160070 } }, "ro%?=81!1l%|r%.%s6    #%vq93,%d0" },
				{ 1, { { 0177300, 0163300 } }, "ro%?=81!1l%|r%.     %Sw%g3" },
				{ 1, { { 0170070, 0160020 } }, "rox%?=81!1l%|r%.%s6   #%vq93,%d0" },
				{ 1, { { 0170070, 0160060 } }, "rox%?=81!1l%|r%.%s6   #%vq93,%d0" },
				{ 1, { { 0177300, 0162300 } }, "rox%?=81!1l%|r%.    %Sw%g3" },
				{ 1, { { 0177777, 0047164 } }, "rtd     #%idw" },
				{ 1, { { 0177760, 0003300 } }, "rtm     %r0" },
				{ 1, { { 0177777, 0047163 } }, "rte" },
				{ 1, { { 0177777, 0047167 } }, "rtr" },
				{ 1, { { 0177777, 0047165 } }, "rts" },
				{ 1, { { 0170770, 0100400 } }, "sbcd    %d0,%d9" },
				{ 1, { { 0170770, 0100410 } }, "sbcd    %a0@-,%a9@-" },
				{ 1, { { 0170300, 0050300 } }, "s%c8     %Sb%g4" },
				{ 1, { { 0177777, 0047162 } }, "stop    #%isw" },
				{ 1, { { 0170400, 0110000 } }, "sub%s6    %g1,%d9" },
				{ 1, { { 0170400, 0110400 } }, "sub%s6    %d9,%g3" },
				{ 1, { { 0170300, 0110300 } }, "sub%sVwl8    %g1,%a9" }, /* suba */
				{ 1, { { 0177400, 0002000 } }, "sub%s6    #%igS,%g4" }, /* subi */
				{ 1, { { 0170400, 0050400 } }, "subq%s6   #%vq93,%g5" },
				{ 1, { { 0170470, 0110400 } }, "subx%s6   %d0,%d9" },
				{ 1, { { 0170470, 0110410 } }, "subx%s6   %a0@-,%a9@-" },
				{ 1, { { 0177770, 0044100 } }, "swap    %d0" },
				{ 1, { { 0177700, 0045300 } }, "tas     %Sb%g4" },
				{ 1, { { 0177760, 0047100 } }, "trap    #%vu04" },
				{ 1, { { 0170376, 0050372 } }, "trap%c!8%sVwl0%cp8 #%iuS" },
				{ 1, { { 0170377, 0050374 } }, "trap%c!8" },
				{ 1, { { 0177777, 0047166 } }, "trapv" },
/* ick, hate having to split tst according to size...disallowing immediate mode for tstb is why. */
/* not sure tstb really does disallow immediate mode; table and text in book disagree. */
				{ 1, { { 0177700, 0045000 } }, "tst%sb    %ga" },
				{ 1, { { 0177400, 0045000 } }, "tst%sv?wl?6    %g1" },
				{ 1, { { 0177770, 0047130 } }, "unlk    %a0" },
				{ 1, { { 0170770, 0100600 } }, "unpk    %d0,%d9,#%ixw" },
				{ 1, { { 0170770, 0100610 } }, "unpk    %a0@-,%a9@-,#%ixw" },
				};
int Machine_m68k_ninstrs = sizeof(Machine_m68k_instrs) / sizeof(Machine_m68k_instrs[0]);

static INSTR _cpinst_def[] = { { 1, { { 0170600, 0170200 } }, "CP%vu93bCC  cond=%vu06 %?=61!1long%|word%." },
			       { 1, { { 0170700, 0170500 } }, "CP%vu93restore %Sw%gb" },
			       { 1, { { 0170700, 0170400 } }, "CP%vu93save %Sw%gc" },
			       { 2, { { 0170770, 0170110 }, { 0177700, 0000000 } }, "CP%vu93dbCC cond=%vu(10)6 %d0" },
			       { 2, { { 0170700, 0170000 }, { 0000000, 0000000 } }, "CP%vu93gen  cmd=%vx(10)(10) ea=<m%vu33,r%vu03>" },
			       { 2, { { 0170700, 0170100 }, { 0177700, 0000000 } }, "CP%vu93sCC  cond=%vu(10)6 %Sb%g4" },
			       { 2, { { 0170776, 0170172 }, { 0177700, 0000000 } }, "CP%vu93trapCC cond=%vu(10)6 %?=01!1long%|word%." },
			       { 2, { { 0170777, 0170174 }, { 0177700, 0000000 } }, "CP%vu93trapCC cond=%vu(10)6 none" },
			       };
static INSTR _6888x[] = { { 2, { { 0177777, 0171000 }, { 0160177, 0000030 } }, "fabs    fp%vu(1A)3%?=(1A)3(17)3%|,fp%vu(17)3%." },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040030 } }, "fabs%sf(1A)   %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000034 } }, "facos   fp%vu(1A)3%?=(1A)3(17)3%|,fp%vu(17)3%." },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040034 } }, "facos%sf(1A)  %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000042 } }, "fadd    fp%vu(1A)3,fp%vu(17)3" },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040042 } }, "fadd%sf(1A)   %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000014 } }, "fasin   fp%vu(1A)3%?=(1A)3(17)3%|,fp%vu(17)3%." },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040014 } }, "fasin%sf(1A)  %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000012 } }, "fatan   fp%vu(1A)3%?=(1A)3(17)3%|,fp%vu(17)3%." },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040012 } }, "fatan%sf(1A)  %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000015 } }, "fatanh  fp%vu(1A)3%?=(1A)3(17)3%|,fp%vu(17)3%." },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040015 } }, "fatanh%sf(1A) %g2,fp%vu(17)3" },
			  { 1, { { 0177600, 0171200 } }, "fb%Fc0  %?=61!1%Tl%|%Tw%." },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000070 } }, "fcmp    fp%vu(1A)3,fp%vu(17)3" },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040070 } }, "fcmp%sf(1A)   %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000035 } }, "fcos    fp%vu(1A)3%?=(1A)3(17)3%|,fp%vu(17)3%." },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040035 } }, "fcos%sf(1A)   %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000031 } }, "fcosh   fp%vu(1A)3%?=(1A)3(17)3%|,fp%vu(17)3%." },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040031 } }, "fcosh%sf(1A)  %g2,fp%vu(17)3" },
			  { 2, { { 0177770, 0171110 }, { 0177700, 0000000 } }, "fdb%Fc(10) %d0,%Tw" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000040 } }, "fdiv    fp%vu(1A)3,fp%vu(17)3" },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040040 } }, "fdiv%sf(1A)   %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000020 } }, "fetox   fp%vu(1A)3%?=(1A)3(17)3%|,fp%vu(17)3%." },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040020 } }, "fetox%sf(1A)  %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000010 } }, "fetoxm1 fp%vu(1A)3%?=(1A)3(17)3%|,fp%vu(17)3%." },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040010 } }, "fetoxm1%sf(1A) %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000036 } }, "fgetexp fp%vu(1A)3%?=(1A)3(17)3%|,fp%vu(17)3%." },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040036 } }, "fgetexp%sf(1A) %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000037 } }, "fgetman fp%vu(1A)3%?=(1A)3(17)3%|,fp%vu(17)3%." },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040037 } }, "fgetman%sf(1A) %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000001 } }, "fint    fp%vu(1A)3%?=(1A)3(17)3%|,fp%vu(17)3%." },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040001 } }, "fint%sf(1A)   %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000003 } }, "fintrz  fp%vu(1A)3%?=(1A)3(17)3%|,fp%vu(17)3%." },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040003 } }, "fintrz%sf(1A) %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000025 } }, "flog10  fp%vu(1A)3%?=(1A)3(17)3%|,fp%vu(17)3%." },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040025 } }, "flog10%sf(1A) %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000026 } }, "flog2   fp%vu(1A)3%?=(1A)3(17)3%|,fp%vu(17)3%." },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040026 } }, "flog2%sf(1A)  %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000024 } }, "flogn   fp%vu(1A)3%?=(1A)3(17)3%|,fp%vu(17)3%." },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040024 } }, "flogn%sf(1A)  %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000006 } }, "flognp1 fp%vu(1A)3%?=(1A)3(17)3%|,fp%vu(17)3%." },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040006 } }, "flognp1%sf(1A) %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000041 } }, "fmod    fp%vu(1A)3,fp%vu(17)3" },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040041 } }, "fmod%sf(1A)   %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000000 } }, "fmove   fp%vu(1A)3,fp%vu(17)3" },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040000 } }, "fmove%sf(1A)  %g2,fp%vu(17)3" },
			  { 2, { { 0177700, 0171000 }, { 0160000, 0060000 } }, "%?=(1A)2!3%X%.fmove%sf(1A)  fp%vu(17)3,%g2" },
			  { 2, { { 0177700, 0171000 }, { 0166000, 0066000 } }, "fmove%sp  fp%vu(17)3,%g4,%?=(1C)1!1%d(14)%?=(10)4!0%|%X%.%|#%vd(10)7%." },
			  { 2, { { 0177700, 0171000 }, { 0177777, 0102000 } }, "fmovel  %Sl%g1,fpiar" },
			  { 2, { { 0177700, 0171000 }, { 0177777, 0104000 } }, "fmovel  %Sl%g2,fpsr" },
			  { 2, { { 0177700, 0171000 }, { 0177777, 0110000 } }, "fmovel  %Sl%g2,fpcr" },
			  { 2, { { 0177700, 0171000 }, { 0177777, 0122000 } }, "fmovel  fpiar,%Sl%g5" },
			  { 2, { { 0177700, 0171000 }, { 0177777, 0124000 } }, "fmovel  fpsr,%Sl%g4" },
			  { 2, { { 0177700, 0171000 }, { 0177777, 0130000 } }, "fmovel  fpcr,%Sl%g4" },
			  { 2, { { 0177777, 0171000 }, { 0176000, 0056000 } }, "fmovecr #%vx(10)7[%Fr(10)],fp%vu(17)3" },
			  { 2, { { 0177700, 0171000 }, { 0177400, 0150000 } }, "fmovemx %Sx%gb,#%vM-(10)8" },
			  { 2, { { 0177700, 0171000 }, { 0177400, 0154000 } }, "fmovemx %Sx%gb,%d(14)%?=(10)4!0%|%X%.%?=(17)1!0%|%X%." },
			  { 2, { { 0177770, 0171040 }, { 0177400, 0160000 } }, "fmovemx #%vM+(10)8,%a0@-" },
			  { 2, { { 0177770, 0171040 }, { 0177400, 0164000 } }, "fmovemx %d(14)%?=(10)4!0%|%X%.%?=(17)1!0%|%X%.,%a0@-" },
			  { 2, { { 0177700, 0171000 }, { 0177400, 0170000 } }, "fmovemx %?=33!3%X%.%Sx%gb,#%vM-(10)8" },
			  { 2, { { 0177700, 0171000 }, { 0177400, 0174000 } }, "fmovemx %?=33!3%X%.%Sx%gb,%d(14)%?=(10)4!0%|%X%.%?=(17)1!0%|%X%." },
			  { 2, { { 0177700, 0171000 }, { 0177777, 0142000 } }, "fmoveml %Sl%g1,fpiar" },
			  { 2, { { 0177700, 0171000 }, { 0177777, 0144000 } }, "fmoveml %Sl%g2,fpsr" },
			  { 2, { { 0177700, 0171000 }, { 0177777, 0146000 } }, "fmoveml %?=33!0%X%.%Sl%g2,fpsr/fpiar" },
			  { 2, { { 0177700, 0171000 }, { 0177777, 0150000 } }, "fmoveml %Sl%g2,fpcr" },
			  { 2, { { 0177700, 0171000 }, { 0177777, 0152000 } }, "fmoveml %?=33!0%X%.%Sl%g2,fpcr/fpiar" },
			  { 2, { { 0177700, 0171000 }, { 0177777, 0154000 } }, "fmoveml %?=33!0%X%.%Sl%g2,fpcr/fpsr" },
			  { 2, { { 0177700, 0171000 }, { 0177777, 0156000 } }, "fmoveml %?=33!0%X%.%Sl%g2,fpcr/fpsr/fpiar" },
			  { 2, { { 0177700, 0171000 }, { 0177777, 0162000 } }, "fmoveml fpiar,%Sl%g1" },
			  { 2, { { 0177700, 0171000 }, { 0177777, 0164000 } }, "fmoveml fpsr,%Sl%g2" },
			  { 2, { { 0177700, 0171000 }, { 0177777, 0166000 } }, "fmoveml fpsr/fpiar,%?=33!0%X%.%Sl%g2" },
			  { 2, { { 0177700, 0171000 }, { 0177777, 0170000 } }, "fmoveml fpcr,%Sl%g2" },
			  { 2, { { 0177700, 0171000 }, { 0177777, 0172000 } }, "fmoveml fpcr/fpiar,%?=33!0%X%.%Sl%g2" },
			  { 2, { { 0177700, 0171000 }, { 0177777, 0174000 } }, "fmoveml fpcr/fpsr,%?=33!0%X%.%Sl%g2" },
			  { 2, { { 0177700, 0171000 }, { 0177777, 0176000 } }, "fmoveml fpcr/fpsr/fpiar,%?=33!0%X%.%Sl%g2" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000043 } }, "fmul    fp%vu(1A)3,fp%vu(17)3" },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040043 } }, "fmul%sf(1A)   %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000032 } }, "fneg    fp%vu(1A)3%?=(1A)3(17)3%|,fp%vu(17)3%." },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040032 } }, "fneg%sf(1A)   %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171200 }, { 0177777, 0000000 } }, "fnop" }, /* fbf .+2 */
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000045 } }, "frem    fp%vu(1A)3,fp%vu(17)3" },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040045 } }, "frem%sf(1A)   %g2,fp%vu(17)3" },
			  { 1, { { 0177700, 0171500 } }, "frestore %Sb%gb" },
			  { 1, { { 0177700, 0171400 } }, "fsave   %Sb%gc" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000046 } }, "fscale  fp%vu(1A)3,fp%vu(17)3" },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040046 } }, "fscale%sf(1A) %g2,fp%vu(17)3" },
			  { 2, { { 0177700, 0171100 }, { 0177700, 0000000 } }, "fs%Fc(10)  %Sb%g4" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000044 } }, "fsgldiv fp%vu(1A)3,fp%vu(17)3" },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040044 } }, "fsgldiv%sf(1A) %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000047 } }, "fsglmul fp%vu(1A)3,fp%vu(17)3" },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040047 } }, "fsglmul%sf(1A) %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000016 } }, "fsin    fp%vu(1A)3%?=(1A)3(17)3%|,fp%vu(17)3%." },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040016 } }, "fsin%sf(1A)   %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160170, 0000060 } }, "fsincos fp%vu(1A)3,fp%vu(10)3:fp%vu(17)3" },
			  { 2, { { 0177700, 0171000 }, { 0160170, 0040060 } }, "fsincos%sf(1A) %g2,fp%vu(10)3:fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000002 } }, "fsinh   fp%vu(1A)3%?=(1A)3(17)3%|,fp%vu(17)3%." },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040002 } }, "fsinh%sf(1A)  %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000004 } }, "fsqrt   fp%vu(1A)3%?=(1A)3(17)3%|,fp%vu(17)3%." },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040004 } }, "fsqrt%sf(1A)  %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000050 } }, "fsub    fp%vu(1A)3,fp%vu(17)3" },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040050 } }, "fsub%sf(1A)   %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000017 } }, "ftan    fp%vu(1A)3%?=(1A)3(17)3%|,fp%vu(17)3%." },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040017 } }, "ftan%sf(1A)   %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000011 } }, "ftanh   fp%vu(1A)3%?=(1A)3(17)3%|,fp%vu(17)3%." },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040011 } }, "ftanh%sf(1A)  %g2,fp%vu(17)3" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000022 } }, "ftentox fp%vu(1A)3%?=(1A)3(17)3%|,fp%vu(17)3%." },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040022 } }, "ftentox%sf(1A) %g2,fp%vu(17)3" },
			  { 2, { { 0177776, 0171172 }, { 0177700, 0000000 } }, "ftrap%Fc(10) #%?=01!1%igl%|%igw%." },
			  { 2, { { 0177777, 0171174 }, { 0177700, 0000000 } }, "ftrap%F!c(10)" },
			  { 2, { { 0177777, 0171000 }, { 0161777, 0000072 } }, "ftst    fp%vu(1A)3" },
			  { 2, { { 0177777, 0171000 }, { 0161777, 0040072 } }, "ftst%sf(1A)   %g2" },
			  { 2, { { 0177777, 0171000 }, { 0160177, 0000021 } }, "ftwotox fp%vu(1A)3%?=(1A)3(17)3%|,fp%vu(17)3%." },
			  { 2, { { 0177700, 0171000 }, { 0160177, 0040021 } }, "ftwotox%sf(1A) %g2,fp%vu(17)3" },
			  };
static INSTR _040cp2[] = { { 1, { { 0177440, 0172000 } }, "cinv%?=32!0%X%.%?=32!1l%.%?=32!2p%.%?=32!3a%.   %?=62!0neither%.%?=62!1data%.%?=62!2instr%.%?=62!3both%.%?=32!3%|,%a0@%." },
			   { 1, { { 0177440, 0172040 } }, "cpush%?=32!0%X%.%?=32!1l%.%?=32!2p%.%?=32!3a%.  %?=62!0neither%.%?=62!1data%.%?=62!2instr%.%?=62!3both%.%?=32!3%|,%a0@%." },
			   };
INSTR *Machine_m68k_cptbl[8] = { &_cpinst_def[0],
				 &_6888x[0],
				 &_040cp2[0],
				 &_cpinst_def[0],
				 &_cpinst_def[0],
				 &_cpinst_def[0],
				 &_cpinst_def[0],
				 &_cpinst_def[0] };
int Machine_m68k_ncptbl[8] = { sizeof(_cpinst_def) / sizeof(_cpinst_def[0]),
			       sizeof(_6888x) / sizeof(_6888x[0]),
			       sizeof(_040cp2) / sizeof(_040cp2[0]),
			       sizeof(_cpinst_def) / sizeof(_cpinst_def[0]),
			       sizeof(_cpinst_def) / sizeof(_cpinst_def[0]),
			       sizeof(_cpinst_def) / sizeof(_cpinst_def[0]),
			       sizeof(_cpinst_def) / sizeof(_cpinst_def[0]),
			       sizeof(_cpinst_def) / sizeof(_cpinst_def[0]) };

#ifdef MACHINE_M68K_MAKETABLE

/* This code is old and not usable with the current table format */

#include <stdio.h>

#define Instrs Machine_m68k_instrs

#define NINSTRS (sizeof(Instrs)/sizeof(Instrs[0]))

static int restrictfail_s(unsigned short int opc, char c, int *szp)
{
 const char *vec;
 int v;
 int sz;

 if (! szp) szp = &sz;
 vec = "bwl?";
 switch (c)
  { case '6':
       v = opc >> 6;
       break;
    case 'c':
       v = opc >> 12;
       vec = "?blw";
       break;
    case 'b': *szp = 1; return(0); break;
    case 'w': *szp = 2; return(0); break;
    case 'l': *szp = 4; return(0); break;
    default:
       abort();
       break;
  }
 switch (vec[v&3])
  { case 'b': *szp = 1; return(0); break;
    case 'w': *szp = 2; return(0); break;
    case 'l': *szp = 4; return(0); break;
  }
 return(1);
}

static int restrictfail_g(unsigned short int opc, int sz, char mode, char loc)
{
 int m;
 int r;

 if (loc == '6')
  { m = (opc >> 6) & 7;
    r = (opc >> 9) & 7;
  }
 else
  { m = (opc >> 3) & 7;
    r = (opc     ) & 7;
  }
#define DATA (m!=1)
#define MEMORY (m>=2)
#define CONTROL ((m==2)||(m==5)||(m==6)||((m==7)&&(r<4)))
#define ALTERABLE ((m<7)||(r<=1))
#define ADDRREGDIRECT (m==1)
#define STATUSREGISTER ((m==7)&&(r==4))
 switch (mode)
  { case '1':
       /* anything, except address register direct if byte */
       return((sz==1)&&ADDRREGDIRECT);
       break;
    case '2':
       /* any data mode: anything but address register direct */
       return(!DATA);
       break;
    case '3':
       /* alterable memory: mode 2/3/4/5/6, or 7:0/1 */
       return(!(MEMORY&&ALTERABLE));
       break;
    case '4':
       /* alterable data: same as '3' except mode 0 is allowed */
       return(!(DATA&&ALTERABLE));
       break;
    case '5':
       /* alterable modes, except address register direct if byte */
       return((ADDRREGDIRECT&&(sz==1))||!ALTERABLE);
       break;
    case '6':
       /* data alterable or status register */
       return(!(DATA&&ALTERABLE)&&!STATUSREGISTER);
       break;
    case '7':
       /* control */
       return(!CONTROL);
       break;
    case '8':
       /* alterable control */
       return(!(CONTROL&&ALTERABLE));
       break;
  }
 abort();
#undef DATA
#undef MEMORY
#undef CONTROL
#undef ALTERABLE
#undef ADDRREGDIRECT
}

static int restrictfail_c(unsigned short int opc, char loc)
{
 int cond;

 switch (loc)
  { case '8': cond = (opc >> 8) & 15; break;
    default: abort(); break;
  }
 return(cond<2);
}

static int passrestrict(unsigned short int opc, const char *dp)
{
 int sz;
 int got_M;

 got_M = 0;
 while (*dp)
  { if (*dp++ != '%') continue;
    switch (*dp++)
     { case 'C':
	  switch (*dp++)
	   { case 't': case 'f': break;
	     default: abort(); break;
	   }
	  break;
       case 'S':
       case 'T':
       case 't':
	  break;
       case 'a':
       case 'd':
	  switch (*dp++)
	   { case '0': case '9': break;
	     default: abort(); break;
	   }
	  break;
       case 'c':
	  if (restrictfail_c(opc,*dp++)) return(0);
	  break;
       case 'M':
	  got_M = 1;
	  break;
       case 'm':
	  if (! got_M) abort();
	  switch (*dp++)
	   { case '+': case '-': break;
	     default: abort(); break;
	   }
	  break;
       case 'q':
	  if (*dp++ != '9') abort();
	  break;
       case 'v':
	  switch (*dp++)
	   { case 's': case 'u': break;
	     default: abort(); break;
	   }
	  if (*dp++ != '0') abort();
	  switch (*dp++)
	   { case '4': case '8': break;
	     default: abort(); break;
	   }
	  break;
       case 's':
	  if (restrictfail_s(opc,*dp++,0)) return(0);
	  break;
       case 'g':
	  if (restrictfail_s(opc,dp[0],&sz)) return(0);
	  if (restrictfail_g(opc,sz,dp[1],dp[2])) return(0);
	  dp += 3;
	  break;
       case 'i':
	  switch (*dp++)
	   { case 'd': case 'u': case 'x': break;
	     default: abort(); break;
	   }
	  if (restrictfail_s(opc,*dp++,0)) return(0);
	  break;
       default:
	  abort();
	  break;
     }
  }
 return(1);
}

void main(void);
void main(void)
{
 int i;
 int j;
 int k;
 INSTR *ip;

 for (i=0;i<65536;i++)
  { if ((i & 0xff) == 0)
     { printf("static short int v%d[256]={\n"/*}*/,i>>8);
       if ((i & 0xfff) == 0)
	{ fprintf(stderr,"%x",i>>12);
	  fflush(stderr);
	}
     }
    k = -1;
    for (j=0;j<NINSTRS;j++)
     { ip = &Instrs[j];
       if (((i & ip->mask) == ip->cmp) && passrestrict(i,ip->desc))
	{ if (k >= 0)
	   { fprintf(stderr,"%07o matches both <%07o %07o %s> and <%07o %07o %s>\n",i,ip->mask,ip->cmp,ip->desc,Instrs[k].mask,Instrs[k].cmp,Instrs[k].desc);
	     exit(1);
	   }
	  k = j;
	}
     }
    printf("%d,\n",k);
    if ((i & 0xff) == 0xff) printf(/*{*/"};\n");
  }
 fprintf(stderr,"\n");
 printf("short int *Machine_m68k_init[256]={\n"/*}*/);
 for (i=0;i<256;i++) printf("&v%d[0],\n",i);
 printf(/*{*/"};\n");
 exit(0);
}

#endif