register numbers:
	0	1	2	3	4	5	6	7
8bit	AL	CL	DL	BL	AH	CH	DH	BH
16bit	AX	CX	DX	BX	SP	BP	SI	DI
32bit	EAX	ECX	EDX	EBX	ESP	EBP	ESI	EDI
seg	ES	CS	SS	DS	FS	GS
fp	ST0	ST1	ST2	ST3	ST4	ST5	ST6	ST7
mmx	MM0	MM1	MM2	MM3	MM4	MM5	MM6	MM7
ctl	CR0		CR2	CR3	CR4
dbg	DR0	DR1	DR23	DR3			DR6	DR7
test				TR3	TR4	TR5	TR6	TR7

condition codes:
O	 0			NO	 1
C	 2	B, NAE		NC	 3	NB,AE
Z	 4	E		NZ	 5	NE
BE	 6	NA		A	 7	NBE
S	 8			NS	 9
PE	10	P		PO	11	NP
L	12	NGE		GE	13	NL
LE	14	NG		G	15	NLE

/r = ModRM, EA taken from r/m or mem operand,
	spare field = reg value of register operand
/0 /1 ... /7 = ModRM, EA taken from r/m or mem operand,
	spare field = 0 to 7, per digit

ModRM byte: mm sss rrr
mm = mod, 0 to 3
sss = spare
rrr = r/m
mm = 11: register, r/m field gives register number, no further bytes
mm = 00,01,10: regs+disp
	mm gives displ size
		mm = 00: no displacement
		mm = 01: one byte
		mm = 10: two or four bytes, per asize (67 prefix)
	16-bit asize:
		r/m gives regs added to displacement:
			r/m = 000: BX+SI
			r/m = 001: BX+DI
			r/m = 010: BP+SI
			r/m = 011: BP+DI
			r/m = 100: SI
			r/m = 101: DI
			r/m = 110: BP
			r/m = 111: BX
	32-bit asize:
		r/m != 100: 32-bit reg r/m added to displacement
		r/m = 100: SIB byte present: ss iii bbb
		ss = scale; index value is << by scale before adding
		iii = index; register number of index register
			(exception: 100 -> none; ESP cannot be used)
		bbb = base; register number of base register
	displacement follows SIB byte, if any
special cases:
	16-bit asize:
		mm=00 r/m=110 -> not [BP], but [disp16]
	32-bit asize:
		mm=00 r/m=101 -> not [EBP] but [disp32]
		mm=00 r/m=100 base=101 -> not [EBP+index] but [disp32+index]

i8 = immediate data, 8 bits
i16 = immediate data, 16 bits
i32 = immediate data, 32 bits
r16 = relative offset, 16 bits
r32 = relative offset, 32 bits
iA, r/mO, etc: A or O is 16 or 32, according as asize or osize is 16 or 32.
O(reg1,reg2) = reg1 or reg2, according as osize is 16 or 32
A(reg1,reg2) = reg1 or reg2, according as asize is 16 or 32
<nn>+r = <nn> plus value of register argument
<nn>+cc = <nn> plus value of condition code

00 /r		ADD	r/m8, reg8
01 /r		ADD	r/mO, regO
02 /r		ADD	reg8, r/m8
03 /r		ADD	regO, r/mO
04 i8		ADD	AL, i8
05 iO		ADD	O(AX,EAX), iO
06		PUSH	ES
07		POP	ES
08 /r		OR	r/m8, reg8
09 /r		OR	r/mO, regO
0a /r		OR	reg8, r/m8
0b /r		OR	regO, r/mO
0c i8		OR	AL, i8
0d iO		OR	O(AX,EAX), iO
0e		PUSH	CS
0f 00 /0	SLDT	r/m16
0f 00 /1	STR	r/m16
0f 00 /2	LLDT	r/m16
0f 00 /3	LTR	r/m16
0f 00 /4	VERR	r/m16
0f 00 /5	VERW	r/m16
0f 01 /0	SGDT	mem
0f 01 /1	SIDT	mem
0f 01 /2	LGDT	mem
0f 01 /3	LIDT	mem
0f 01 /4	SMSW	r/m16
0f 01 /6	LMSW	r/m16
0f 01 /7	INVLPG	mem
0f 02 /r	LAR	rO, r/mO
0f 03 /r	LSL	regO, r/mO
0f 05		LOADALL286
0f 06		CLTS
0f 07		LOADALL
0f 08		INVD
0f 09		WBINVD
0f 10 /r	UMOV	r/m8, reg8
0f 11 /r	UMOV	r/mO, regO
0f 12 /r	UMOV	reg8, r/m8
0f 13 /r	UMOV	regO, r/mO
0f 20 /r	MOV	reg32, CR[0234]
0f 21 /r	MOV	reg32, DR[012367]
0f 22 /r	MOV	CR[0234], reg32
0f 23 /r	MOV	DR[012367], reg32
0f 24 /r	MOV	reg32, TR[34567]
0f 26 /r	MOV	TR[34567], reg32
0f 30		WRMSR
0f 31		RDTSC
0f 32		RDMSR
0f 33		RDPMC
0f 40+cc /r	CMOVcc	regO, r/mO
0f 50 /r	PAVEB	mmxreg, r/m64
0f 51 /r	PADDSIW	mmxreg, r/m64
0f 52 /r	PMAGW	mmxreg, r/m64
0f 54 /r	PDISTIB	mmxreg, mem64
0f 55 /r	PSUBSIW	mmxreg, r/m64
0f 58 /r	PMVZB	mmxreg, mem64
0f 59 /r	PMULHRW	mmxreg, r/m64
0f 5a /r	PMVNZB	mmxreg, mem64
0f 5b /r	PMVLZB	mmxreg, mem64
0f 5c /r	PMVGEZB	mmxreg, mem64
0f 5d /r	PMULHRIW mmxreg, r/m64
0f 5e /r	PMACHRIW mmxreg, mem64
0f 60 /r	PUNPCKLBW mmxreg, r/m64
0f 61 /r	PUNPCKLWD mmxreg, r/m64
0f 62 /r	PUNPCKLDQ mmxreg, r/m64
0f 63 /r	PACKSSWB mmxreg, r/m64
0f 64 /r	PCMPGTB	mmxreg, r/m64
0f 65 /r	PCMPGTW	mmxreg, r/m64
0f 66 /r	PCMPGTD	mmxreg, r/m64
0f 67 /r	PACKUSWB mmxreg, r/m64
0f 68 /r	PUNPCKHBW mmxreg, r/m64
0f 69 /r	PUNPCKHWD mmxreg, r/m64
0f 6a /r	PUNPCKHDQ mmxreg, r/m64
0f 6b /r	PACKSSDW mmxreg, r/m64
0f 6e /r	MOVD	mmxreg, r/m32
0f 6f /r	MOVQ	mmxreg, r/m64
0f 71 /2 i8	PSRLW	mmxreg, i8
0f 71 /4 i8	PSRAW	mmxreg, i8
0f 71 /6 i8	PSLLW	mmxreg, i8
0f 72 /2 i8	PSRLD	mmxreg, i8
0f 72 /4 i8	PSRAD	mmxreg, i8
0f 72 /6 i8	PSLLD	mmxreg, i8
0f 73 /2 i8	PSRLQ	mmxreg, i8
0f 73 /6 i8	PSLLQ	mmxreg, i8
0f 74 /r	PCMPEQB	mmxreg, r/m64
0f 75 /r	PCMPEQW	mmxreg, r/m64
0f 76 /r	PCMPEQD	mmxreg, r/m64
0f 77		EMMS
0f 7e /r	MOVD	r/m32, mmxreg
0f 7f /r	MOVQ	r/m64, mmxreg
0f 80+cc rO	Jcc	NEAR rO
0f 90+cc /x	SETcc/x	r/m8
0f a0		PUSH	FS
0f a1		POP	FS
0f a2		CPUID
0f a3 /r	BT	r/mO, regO
0f a4 /r i8	SHLD	r/mO, regO, i8
0f a5 /r	SHLD	r/mO, regO, CL
0f a6 /r	XBTS	regO, r/mO
0f a7 /r	IBTS	r/mO, regO
0f a8		PUSH	GS
0f a9		POP	GS
0f aa		RSM
0f ab /r	BTS	r/mO, regO
0f ac /r i8	SHRD	r/mO, regO, i8
0f ad /r	SHRD	r/mO, regO, CL
0f af /r	IMUL	regO, r/mO
0f b0 /r	CMPXCHG	r/m8, reg8
0f b1 /r	CMPXCHG	r/mO, regO
0f b2 /r	LSS	rO, mem
0f b3 /r	BTR	r/mO, regO
0f b4 /r	LFS	rO, mem
0f b5 /r	LGS	rO, mem
0f b6 /r	MOVZX	regO, r/m8
0f b7 /r	MOVZX	reg32, r/m16 [o32]
0f ba /4 i8	BT	r/mO, i8
0f ba /5 i8	BTS	r/mO, i8
0f ba /6 i8	BTR	r/mO, i8
0f ba /7 i8	BTC	r/mO, i8
0f bb /r	BTC	r/mO, regO
0f bc /r	BSF	regO, r/mO
0f bd /r	BSR	regO, r/mO
0f be /r	MOVSX	regO, r/m8
0f bf /r	MOVSX	reg32, r/m16 [o32]
0f c0 /r	XADD	r/m8, reg8
0f c1 /r	XADD	r/mO, regO
0f c7 /1	CMPXCHG8B mem
0f c8+r		BSWAP	reg32
0f d1 /r	PSRLW	mmxreg, r/m64
0f d2 /r	PSRLD	mmxreg, r/m64
0f d3 /r	PSRLQ	mmxreg, r/m64
0f d5 /r	PMULLW	mmxreg, r/m64
0f d8 /r	PSUBUSB	mmxreg, r/m64
0f d9 /r	PSUBUSW	mmxreg, r/m64
0f db /r	PAND	mmxreg, r/m64
0f dc /r	PADDUSB	mmxreg, r/m64
0f dd /r	PADDUSW	mmxreg, r/m64
0f df /r	PANDN	mmxreg, r/m64
0f e1 /r	PSRAW	mmxreg, r/m64
0f e2 /r	PSRAD	mmxreg, r/m64
0f e5 /r	PMULHW	mmxreg, r/m64
0f e8 /r	PSUBSB	mmxreg, r/m64
0f e9 /r	PSUBSW	mmxreg, r/m64
0f eb /r	POR	mmxreg, r/m64
0f ec /r	PADDSB	mmxreg, r/m64
0f ed /r	PADDSW	mmxreg, r/m64
0f ef /r	PXOR	mmxreg, r/m64
0f f1 /r	PSLLW	mmxreg, r/m64
0f f2 /r	PSLLD	mmxreg, r/m64
0f f3 /r	PSLLQ	mmxreg, r/m64
0f f5 /r	PMADDWD	mmxreg, r/m64
0f f8 /r	PSUBB	mmxreg, r/m64
0f f9 /r	PSUBW	mmxreg, r/m64
0f fa /r	PSUBD	mmxreg, r/m64
0f fc /r	PADDB	mmxreg, r/m64
0f fd /r	PADDW	mmxreg, r/m64
0f fe /r	PADDD	mmxreg, r/m64
10 /r		ADC	r/m8, reg8
11 /r		ADC	r/mO, regO
12 /r		ADC	reg8, r/m8
13 /r		ADC	regO, r/mO
14 i8		ADC	AL, i8
15 iO		ADC	O(AX,EAX), iO
16		PUSH	SS
17		POP	SS
18 /r		SBB	r/m8, reg8
19 /r		SBB	r/mO, regO
1a /r		SBB	reg8, r/m8
1b /r		SBB	regO, r/mO
1c i8		SBB	AL, i8
1d iO		SBB	O(AX,EAX), iO
1e		PUSH	DS
1f		POP	DS
20 /r		AND	r/m8, reg8
21 /r		AND	r/mO, regO
22 /r		AND	reg8, r/m8
23 /r		AND	regO, r/mO
24 i8		AND	AL, i8
25 iO		AND	O(AX,EAX), iO
27		DAA
28 /r		SUB	r/m8, reg8
29 /r		SUB	r/mO, regO
2a /r		SUB	reg8, r/m8
2b /r		SUB	regO, r/mO
2c i8		SUB	AL, i8
2d iO		SUB	O(AX,EAX), iO
2f		DAS
30 /r		XOR	r/m8, reg8
31 /r		XOR	r/mO, regO
32 /r		XOR	reg8, r/m8
33 /r		XOR	regO, r/mO
34 i8		XOR	AL, i8
35 iO		XOR	O(AX,EAX), iO
37		AAA
38 /r		CMP	r/m8, reg8
39 /r		CMP	r/mO, regO
3a /r		CMP	reg8, r/m8
3b /r		CMP	regO, r/mO
3c ib		CMP	AL, i8
3d iO		CMP	O(AX,EAX), iO
3f		AAS
40+r		INC	regO
48+r		DEC	regO
50+r		PUSH	regO
58+r		POP	regO
60		PUSHAD [o32]
60		PUSHAW [o16]
61		POPAD [o32]
61		POPAW [o16]
62 /r		BOUND	regO, mem
63 /r		ARPL	r/m16, reg16
68 iO		PUSH	iO
69 /r iO	IMUL	regO, r/mO, iO
6a i8		PUSH	i8
6b /r i8	IMUL	regO, r/mO, i8
6c		INSB
6d		INSD [o32]
6d		INSW [o16]
6e		OUTSB
6f		OUTSD [o32]
6f		OUTSW [o16]
70+cc r8	Jcc	SHORT r8
80 /0 i8	ADD	r/m8, i8
80 /1 i8	OR	r/m8, i8
80 /2 i8	ADC	r/m8, i8
80 /3 i8	SBB	r/m8, i8
80 /4 i8	AND	r/m8, i8
80 /5 i8	SUB	r/m8, i8
80 /6 i8	XOR	r/m8, i8
80 /7 i8	CMP	r/m8, i8
81 /0 iO	ADD	r/mO, iO
81 /1 iO	OR	r/mO, iO
81 /2 iO	ADC	r/mO, iO
81 /3 iO	SBB	r/mO, iO
81 /4 iO	AND	r/mO, iO
81 /5 iO	SUB	r/mO, iO
81 /6 iO	XOR	r/mO, iO
81 /7 iO	CMP	r/mO, iO
83 /0 i8	ADD	r/mO, i8
83 /1 i8	OR	r/mO, i8
83 /2 i8	ADC	r/mO, i8
83 /3 ib	SBB	r/mO, i8
83 /4 i8	AND	r/mO, i8
83 /5 i8	SUB	r/mO, i8
83 /6 i8	XOR	r/mO, i8
83 /7 ib	CMP	r/mO, i8
84 /r		TEST	r/m8, reg8
85 /r		TEST	r/mO, regO
86 /r		XCHG	reg8, r/m8
87 /r		XCHG	regO, r/mO
88 /r		MOV	r/m8, reg8
89 /r		MOV	r/mO, regO
8a /r		MOV	reg8, r/m8
8b /r		MOV	regO, r/mO
8c /r		MOV	r/mO, segreg
8d /r		LEA	rO, mem
8e /r		MOV	segreg, r/mO
8f /0		POP	r/mO
90		NOP [XCHG AX,AX or XCHG EAX,EAX]
90+r		XCHG	O(AX,EAX), regO
98		CBW [o16]
98		CWDE [o32]
99		CDQ [o32]
99		CWD [o16]
9a iO i16	CALL	i16:iO
9b		WAIT
9c		PUSHFD [o32]
9c		PUSHFW [o16]
9d		POPFD [o32]
9d		POPFW [o16]
9e		SAHF
9f		LAHF
a0 ow/od	MOV	AL, memoffs8
a1 ow/od	MOV	O(AX,EAX), memoffsO
a2 ow/od	MOV	memoffs8, AL
a3 ow/od	MOV	memoffsO, O(AX,EAX)
a4		MOVSB
a5		MOVSD [o32]
a5		MOVSW [o16]
a6		CMPSB
a7		CMPSD [o32]
a7		CMPSW [o16]
a8 i8		TEST	AL, i8
a9 iO		TEST	O(AX,EAX), iO
aa		STOSB
ab		STOSD [o32]
ab		STOSW [o16]
ac		LODSB
ad		LODSD [o32]
ad		LODSW [o16]
ae		SCASB
af		SCASD [o32]
af		SCASW [o16]
b0+r i8		MOV	reg8, i8
b8+r iO		MOV	regO, iO
c0 /0 i8	ROL	r/m8, i8
c0 /1 i8	ROR	r/m8, i8
c0 /2 i8	RCL	r/m8, i8
c0 /3 i8	RCR	r/m8, i8
c0 /4 i8	SHL	r/m8, i8
c0 /5 i8	SHR	r/m8, i8
c0 /7 i8	SAR	r/m8, i8
c1 /0 i8	ROL	r/mO, i8
c1 /1 i8	ROR	r/mO, i8
c1 /2 i8	RCL	r/mO, i8
c1 /3 i8	RCR	r/mO, i8
c1 /4 i8	SHL	r/mO, i8
c1 /5 i8	SHR	r/mO, i8
c1 /7 i8	SAR	r/mO, i8
c2 i16		RETN	i16
c3		RETN
c4 /r		LES	rO, mem
c5 /r		LDS	rO, mem
c6 /0 i8	MOV	r/m8, i8
c7 /0 iO	MOV	r/mO, iO
c8 i16 i8	ENTER	i16, i8
c9		LEAVE
ca i16		RETF	i16
cb		RETF
cc		INT3
cd i8		INT	i8
ce		INTO
cf		IRETD [o32]
cf		IRETW [o16]
d0 /0		ROL	r/m8, 1
d0 /1		ROR	r/m8, 1
d0 /2		RCL	r/m8, 1
d0 /3		RCR	r/m8, 1
d0 /4		SHL	r/m8, 1
d0 /5		SHR	r/m8, 1
d0 /7		SAR	r/m8, 1
d0 e4		FTST
d1 /0		ROL	r/mO, 1
d1 /1		ROR	r/mO, 1
d1 /2		RCL	r/mO, 1
d1 /3		RCR	r/mO, 1
d1 /4		SHL	r/mO, 1
d1 /5		SHR	r/mO, 1
d1 /7		SAR	r/mO, 1
d2 /0		ROL	r/m8, CL
d2 /1		ROR	r/m8, CL
d2 /2		RCL	r/m8, CL
d2 /3		RCR	r/m8, CL
d2 /4		SHL	r/m8, CL
d2 /5		SHR	r/m8, CL
d2 /7		SAR	r/m8, CL
d3 /0		ROL	r/mO, CL
d3 /1		ROR	r/mO, CL
d3 /2		RCL	r/mO, CL
d3 /3		RCR	r/mO, CL
d3 /4		SHL	r/mO, CL
d3 /5		SHR	r/mO, CL
d3 /7		SAR	r/mO, CL
d4 i8		AAM	i8
d5 i8		AAD	i8
d6		SALC
d7		XLATB
d8 /0		FADD	mem32
d8 /1		FMUL	mem32
d8 /2		FCOM	mem32
d8 /3		FCOMP	mem32
d8 /4		FSUB	mem32
d8 /5		FSUBR	mem32
d8 /6		FDIV	mem32
d8 /7		FDIVR	mem32
d8 c0+r		FADD	fpureg
d8 c8+r		FMUL	fpureg
d8 d0+r		FCOM	fpureg
d8 d8+r		FCOMP	fpureg
d8 e0+r		FSUB	fpureg
d8 e8+r		FSUBR	fpureg
d8 f0+r		FDIV	fpureg
d8 f8+r		FDIVR	fpureg
d9 /0		FLD	mem32
d9 /2		FST	mem32
d9 /3		FSTP	mem32
d9 /4		FLDENV	mem
d9 /5		FLDCW	mem16
d9 /6		FNSTENV	mem
d9 /7		FNSTCW	mem16
d9 c0+r		FLD	fpureg
d9 c8+r		FXCH	fpureg
d9 d0		FNOP
d9 e0		FCHS
d9 e1		FABS
d9 e5		FXAM
d9 e8		FLD1
d9 e9		FLDL2T
d9 ea		FLDL2E
d9 eb		FLDPI
d9 ec		FLDLG2
d9 ed		FLDLN2
d9 ee		FLDZ
d9 f0		F2XM1
d9 f1		FYL2X
d9 f2		FPTAN
d9 f3		FPATAN
d9 f4		FXTRACT
d9 f5		FPREM1
d9 f6		FDECSTP
d9 f7		FINCSTP
d9 f8		FPREM
d9 f9		FYL2XP1
d9 fa		FSQRT
d9 fb		FSINCOS
d9 fc		FRNDINT
d9 fd		FSCALE
d9 fe		FSIN
d9 ff		FCOS
da /0		FIADD	mem32
da /1		FIMUL	mem32
da /2		FICOM	mem32
da /3		FICOMP	mem32
da /4		FISUB	mem32
da /5		FISUBR	mem32
da /6		FIDIV	mem32
da /7		FIDIVR	mem32
da c0+r		FCMOVB	fpureg
da c8+r		FCMOVE	fpureg
da d0+r		FCMOVBE	fpureg
da d8+r		FCMOVU	fpureg
da e9		FUCOMPP
db /0		FILD	mem32
db /2		FIST	mem32
db /3		FISTP	mem32
db /5		FLD	mem80
db /7		FSTP	mem80
db c0+r		FCMOVNB	fpureg
db c8+r		FCMOVNE	fpureg
db d0+r		FCMOVNBE fpureg
db d8+r		FCMOVNU	fpureg
db e0		FNENI
db e1		FNDISI
db e2		FNCLEX
db e3		FNINIT
db e4		FSETPM
db e8+r		FUCOMI	fpureg
db f0+r		FCOMI	fpureg
dc /0		FADD	mem64
dc /1		FMUL	mem64
dc /2		FCOM	mem64
dc /3		FCOMP	mem64
dc /4		FSUB	mem64
dc /5		FSUBR	mem64
dc /6		FDIV	mem64
dc /7		FDIVR	mem64
dc c0+r		FADD	TO fpureg
dc c8+r		FMUL	TO fpureg
dc e0+r		FSUBR	TO fpureg
dc e8+r		FSUB	TO fpureg
dc f0+r		FDIVR	TO fpureg
dc f8+r		FDIV	TO fpureg
dd /0		FLD	mem64
dd /2		FST	mem64
dd /3		FSTP	mem64
dd /4		FRSTOR	mem
dd /6		FNSAVE	mem
dd /7		FNSTSW	mem16
dd c0+r		FFREE	fpureg
dd d0+r		FST	fpureg
dd d8+r		FSTP	fpureg
dd e0+r		FUCOM	fpureg
dd e8+r		FUCOMP	fpureg
de /0		FIADD	mem16
de /1		FIMUL	mem16
de /2		FICOM	mem16
de /3		FICOMP	mem16
de /4		FISUB	mem16
de /5		FISUBR	mem16
de /6		FIDIV	mem16
de /7		FIDIVR	mem16
de c0+r		FADDP	fpureg
de c8+r		FMULP	fpureg
de d9		FCOMPP
de e0+r		FSUBRP	fpureg
de e8+r		FSUBP	fpureg
de f0+r		FDIVRP	fpureg
de f8+r		FDIVP	fpureg
df /0		FILD	mem16
df /2		FIST	mem16
df /3		FISTP	mem16
df /4		FBLD	mem80
df /5		FILD	mem64
df /6		FBSTP	mem80
df /7		FISTP	mem64
df e0		FNSTSW	AX
df e8+r		FUCOMIP	fpureg
df f0+r		FCOMIP	fpureg
e0 r8		LOOPNE	r8, A(CX,ECX)
e1 r8		LOOPE	r8, A(CX,ECX)
e2 r8		LOOP	r8, A(CX,ECX)
e3 r8		JCXZ	r8 [o16]
e3 r8		JECXZ	r8 [o32]
e4 i8		IN	AL, i8
e5 i8		IN	O(AX,EAX), i8
e6 i8		OUT	i8, AL
e7 i8		OUT	i8, O(AX,EAX)
e8 rO		CALL	rO
e9 rO		JMP	rO
ea iO i16	JMP	i16:iO
eb r8		JMP	SHORT r8
ec		IN	AL, DX
ed		IN	O(AX,EAX), DX
ee		OUT	DX, AL
ef		OUT	DX, O(AX,EAX)
f1		INT1
f4		HLT
f5		CMC
f6 /0 i8	TEST	r/m8, i8
f6 /2		NOT	r/m8
f6 /3		NEG	r/m8
f6 /4		MUL	r/m8
f6 /5		IMUL	r/m8
f6 /6		DIV	r/m8
f6 /7		IDIV	r/m8
f7 /0 iO	TEST	r/mO, iO
f7 /2		NOT	r/mO
f7 /3		NEG	r/mO
f7 /4		MUL	r/mO
f7 /5		IMUL	r/mO
f7 /6		DIV	r/mO
f7 /7		IDIV	r/mO
f8		CLC
f9		STC
fa		CLI
fb		STI
fc		CLD
fd		STD
fe /0		INC	r/m8
fe /1		DEC	r/m8
ff /0		INC	r/mO
ff /1		DEC	r/mO
ff /2		CALL	r/mO
ff /3		CALL	FAR memO
ff /4		JMP	NEAR r/mO
ff /5		JMP	FAR mem
ff /6		PUSH	r/mO

8d 04 92		leal   (%edx,%edx,4),%eax
8d 04 42		leal   (%edx,%eax,2),%eax
8d 04 80		leal   (%eax,%eax,4),%eax
ff 34 85 0c 9c 07 00	pushl  0x79c0c(,%eax,4)
e8 15 40 04 00		call   0x5602a
8d 65 f4		leal   0xfffffff4(%ebp),%esp
5b			popl   %ebx
5e			popl   %esi
5f			popl   %edi
c9			leave