promvec (%i0) - arch/sparc/include/bsd_openprom.h 00 0x10010407 04 int pv_romvec_vers 08 int pv_plugin_vers 0c int pv_printrev struct v0mem pv_v0mem "V0: Memory description lists" struct v0mem: 10 struct v0mlist **v0_phystot 14 struct v0mlist **v0_vmprom 18 struct v0mlist *v0_physavail 1c struct nodeops *pv_nodeops struct nodeops: 00 int (*no_nextnode)(int); 04 int (*no_child)(int); 08 int (*no_proplen)(int, char *); 0c int (*no_getprop)(int, char *, void *); 10 int (*no_setprop)(int, chr *, void *, int); 14 char *(*no_nextprop)(int, char *); 20 char **pv_bootstr struct v0devops pv_v0devops; struct v0devops: 24 int (*v0_open)(char *); 28 int (*v0_close)(int); 2c int (*v0_rbdev)(int, int, int, void *); 30 int (*v0_wbdev)(int, int, int, void *); 34 int (*v0_wnet)(int, int, void *); 38 int (*v0_rnet)(int, int, void *); 3c int (*v0_rcdev)(int, int, int, void *); 40 int (*v0_wcdev)(int, int, int, void *); 44 int (*v0_seek)(int, long, int); 48 char *pv_stdin 4c char *pv_stdout above two: 0 for screen/kbd, 1 for ttya, 2 for ttyb 50 int (*pv_getchar)(void); // blocking 54 void (*pv_putchar)(int); // blocking 58 int (*pv_nbgetchar)(void); // nonblocking, -1 on error 5c int (*pv_nbputchar)(int); // nonblocking, -1 on error 60 void (*pv_putstr)(char *, int); // may be very slow 64 void (*pv_reboot)(char *); 68 void (*pv_printf)(const char *, ...); 6c void (*pv_abort)(void); 70 int *pv_ticks; 74 void (*pv_halt)(void); 78 void (**pv_synchook)(void); 7c function pointer to eval a FORTH string 80 struct v0bootargs **pv_v0bootargs; 84 function pointer to get Ethernet MAC struct v2bootargs pv_v2bootargs struct v2bootargs: 88 char **v2_bootpath; 8c char **v2_bootargs; 90 int *v2_fd0; // stdin 94 int *v2_fd1; // stdout strct v2devops pv_v2devops struct v2devops 98 int (*v2_fd_phandle)(int); // instance handle to package handle 9c void *(*v2_malloc)(caddr_t, u_int); a0 void (*v2_free)(caddr_t, u_int); a4 caddr_t (*v2_mmap)(caddr_t, int, u_int, u_int); a8 void (*v2_munmap)(caddr_t, u_int); ac int (*v2_open)(char *); b0 void (*v2_close)(int); b4 int (*v2_read)(int, void *, int); b8 int (*v2_write)(int, void *, int); <-- used for v2_putchar, pass *v2_fd1 as first arg bc int (*v2_seek)(int, int, int); c0 void (*v2_chain)(void); c4 void (*v2_release)(void); Reference MMU: 32-bit virtual address 36-bit physical address 4K pages 3-level map mapping size: 4K, 256K, 16M, 4G Ctx Tbl L 1 L 2 L 3 +------+ +-----+ +-----+ +-----+ Context ---> | Root | ---> | PTD | ---> | PTD | ---> | PTE | | . | | . | | . | | . | | . | | . | | . | | . | +------+ | . | | . | | . | size +-----+ +-----+ +-----+ hardware 256 64 64 dependent entries entries entries [PTD = Page Table Descriptor] L1 or L2 may contain PTE instead of PTD PTD: 31 2 1 0 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | PTP | ET| +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ PTE: 31 8 7 6 5 4 2 1 0 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | PPN |C|M|R| ACC | ET| +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ PTP = page table pointer, physical addr of next-level page table, shifted by 4 bits (low 6 bits of address are 0). PPN = physical page number, high 24 bits of 36-bit physical address If a PTE appears in L1 or L2 table, the low 12 or 6 bits of the PPN field must be zero. C = cacheable M = modified R = referenced ACC = access permissions: ACC User Super 000 RO RO 001 RW RW 010 RX RX 011 RWX RWX 100 X X 101 R RW 110 none RX 111 none RWX ET = entry type: 00 Invalid (VM space not valid) 01 PTD 10 PTE 11 Reserved Probing and flushing is done with an alternative address space. (NetBSD says this is ASI 3.) Addresses in this space look like 31 12 11 8 7 0 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | VFPA | Type | reserved | +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ VFPA = virtual flush/probe address Type = type of object: Type Probe Flush 0000 L3 entry L3 PTE 0001 L2 entry L2/L3 PTE/PTDs 0010 L1 entry L1/L2/L3 PTE/PTDs 0011 L0 entry L0/L1/L2/L3 PTE/PTDs 0100 Ln entry All PTEs/PTDs other reserved reserved A flush operation removes from the TLB. Supervisor PTEs are always removed; user PTEs are removed if context tag matches. (May always remove additional entries.) The difference between 0011 and 0100 flushes is the context tag. These are done with stores. Data stored is ignored. PTE removal criterion: 0000 (ACC>=6 or contexts equal) and VA[31:12] equal 0001 (ACC>=6 or contexts equal) and VA[31:18] equal 0010 (ACC>=6 or contexts equal) and VA[31:24] equal 0011 ACC<=5 and contexts equal 0100 Always PTD removal criterion: 0000 Contexts equal and VA[31:12] equal 0001 Contexts equal and VA[31:18] equal 0010 Contexts equal and VA[31:24] equal 0011 Contexts equal 0100 Always A probe returns an entry from TLB or from table, or error. These are done with loads. Error consists of: - A non-PTD is found before the level probed is reached. - A memory error occurs. No exception is signaled, but fault registers are updated. On either error, zero is returned. Otherwise, the entry is returned. Actions: 0 return 0 * return entry > examine next-level table Note the peculiar type ordering in this table. Copied from above: 2 3 0 1 PTE res'd inval PTD L0 type L1 type L2 type L3 type Type 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 0000 0 0 0 > 0 0 0 > 0 0 0 > * 0 * 0 0001 0 0 0 > 0 0 0 > * 0 * * --- 0010 0 0 0 > * 0 * * --- --- 0011 * 0 * * --- --- --- 0100 * 0 0 > * 0 0 > * 0 0 > * 0 0 0 MMU has five registers: Control - CSR Context - current process's context Context Table Pointer - base of context table Fault Address - address causing MMU fault Fault Status - details of fault MMU register access (presumably via ASI - NetBSD says ASI 4) 000000xx Control 000001xx Context Table Pointer 000002xx Context 000003xx Fault Status 000004xx Fault Address 000005xx to Reserved 00000fxx 000010xx to Unassigned ffffffxx Control: 31 28 27 24 23 8 7 6 2 1 0 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | IMPL | VER | SC | | res'd | |E| +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ PSO NF IMPL - RO implementation identifier VER - RO version identifier SC - implementation-defined system control bits; NetBSD has different descriptions for these depending on hardware (eg, turbosparc versus viking versus hypersparc). PSO - controls whether memory model is 0 Total Store Order 1 Partial Store Order NF - no fault 0 Faults update FSR and FAR and fault CPU normally 1 ASI 9 (super inst) accesses handled as if NF=0 Other accesses update FSR and FAR but no fault Clearing NF does not fault the CPU E - global enable: 0 Disabled 1 Enabled When disabled, physical address out equals virtual address in; upper 4 bits of physical address are zero. All addresses are non-cacheable. On reset, PSO and E are set to 0. Context Table Pointer: Physical address of context table, right-shifted 4 bits. This must be 6-bit (32-byte) aligned; the low two bits of the register are reserved. However, the context table must also be aligned on a natural boundary for its size; for example, if contexts are 8 bits, the table has 256 entries, each 4 bytes, for 1024 bytes; it must then be aligned on a 1024-byte boundary. Context: Simply stores a context number. The number of supported contexts must be a power of two. Fault Status (RO): 31 18 17 10 9 8 7 5 4 2 1 0 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | reserved | EBE | L | AT | FT | | | +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ FAV OW EBE - External Bus Error, implementaiton-dependent L - Level: level of PTE that caused an EBE fault 0 Context table 1 L1 page table 2 L2 page table 3 L3 page table AT - Access type which faulted: 0 Load from user data 1 Load from supervisor data 2 Load/execute from user instruction 3 Load/execute from supervisor instruction 4 Store to user data 5 Store to supervisor data 6 Store to user instruction 7 Store to supervisor instruction (6 and 7 can be caused by sta instructions) FT - Fault type 0 None 1 Invalid address 2 Protection 3 Privilege violation 4 Translation 5 Access bus 6 Internal 7 Reserved Generated FT when: PTE.V=0 ----PTE.V=1---- PTE.ACC = AT 0 1 2 3 4 5 6 7 0 1 - - - - 2 - 3 3 1 1 - - - - 2 - - - 2 1 2 2 - - - 2 3 3 3 1 2 2 - - - 2 - - 4 1 2 0 2 0 2 2 3 3 5 1 2 - 2 - 2 - 2 - 6 1 2 2 2 - 2 2 3 3 7 1 2 2 2 - 2 2 2 - Translation error means: EBE occurs, PTD found in L3 table, or an entry as ET 3 (reserved). Access bus error is an external memory error *not* during a PTE walk. FAV - Fault Address Valid - FAR is valid. OW - Overwrite: FSR has been written more than ocne by faults of the same class since it was read. Fault Address: Records faulting VA, or at least the VPN bits of it. ASIs: 0 reserved 1 unassigned 2 unassigned ("system registers") 3 MMU flush/probe 4 MMU registers 5 MMU diagnostics 6 MMU diagnostics 7 MMU diagnostics 8 user instruction 9 supervisor instruction a user data b supervisor data c cache tag for i$ d cache data for i$ e cache tag for d$ or combined i/d $ f cache data for d$ or combined i/d $ 10 flush combined i/d $ (page) 11 flush combined i/d $ (segment) 12 flush combined i/d $ (region) 13 flush combined i/d $ (context) 14 flush combined i/d $ (user) 15 reserved 16 reserved 17 block copy 18 flush i$ (page) 19 flush i$ (segment) 1a flush i$ (region) 1b flush i$ (context) 1c flush i$ (user) 1d reserved 1e reserved 1f block fill 20-2f MMU pass-through (high four bits of physical address are low four bits of ASI) 30-7f unassigned 80-ff reserved